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US 8,772,751 B2Granted
Variable resistance semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsAkira Takashima, Daisuke Matsushita, Takashi Yamauchi, Yuuichi Kamimuta, Hidenori Miyagawa
Life of this patent
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Abstract
According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0≦x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.
Claims19
A memory device comprising:
- a first electrode of a resistance change element which comprises a crystallized SixGe1-x layer (0≦x<1);
- a second electrode of a resistance change element which comprises a metal element;
- a variable resistance part between the first and second electrode, the part comprising an amorphous Si layer;
- a control circuit controlling a filament in the amorphous Si layer, the filament comprising the metal element, and
- an inter layer between the SixGe1-x layer and the amorphous Si layer, the inter layer isolating crystal structures of the SixGe1-x layer and the amorphous Si layer from each other.
2 more elements
A memory device comprising:
- a first electrode including a crystallized SixGe1-x layer (0≦x<1);
- a second electrode including a metal element;
- a variable resistance part between the first and second electrode, the part including an amorphous Si layer;
- and
- a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element,
- wherein the SixGe1-x layer (except for x=0) has a concentration gradient in its composition in which a Si concentration is highest at a portion closest to the amorphous Si.
3 more elements
Dependencies are inferred from the claim text.