Method of forming an integrated circuit

A method of forming an integrated circuit, the method comprising:

• providing a first material layer;
• forming a second material layer on the first material layer;
• forming a patterned mask layer having a plurality of first features with a first pitch P1 on the second material layer, wherein each first feature has a first space S1 to adjacent first features;
• etching the second material layer by using the patterned mask layer as a mask to form the first features in the second material layer and expose a portion of a top surface of the first material layer;
• widening the first space S1 in the patterned mask layer to a space ST;
• after widening the first space S1, implanting a plurality of dopants into the second material layer not covered by the patterned mask layer;
• removing the patterned mask layer to expose un-doped second material layer;
• selectively removing the un-doped second material layer to form a plurality of second features with a second pitch P2 in the second material layer, wherein the second pitch P2 is substantially one-half of the first pitch P1.

A method of forming an integrated circuit, the method comprising:

• providing a first material layer;
• forming a silicon layer on the first material layer;
• forming a patterned mask layer having a plurality of first features with a first pitch P1 on the silicon layer;
• patterning the silicon layer by using the patterned mask layer as a mask to form the first features in the silicon layer and expose a portion of a top surface of the first material layer;
• trimming the patterned mask layer after patterning the silicon layer to form a trimmed patterned mask layer;
• substantially vertically implanting a plurality of dopants into the silicon layer not covered by the trimmed patterned mask layer;
• removing the trimmed patterned mask layer to expose an un-doped silicon layer;
• selectively removing the un-doped silicon layer with an etchant to form a plurality of second features with a second pitch P2 in the silicon layer, wherein the second pitch P2 is smaller than the first pitch P1.