Technique for forming a dielectric interlayer above a structure including closely spaced lines
AssigneeGlobalfoundries Inc.
InventorsHartmut Ruelke, Christof Streck, Kai Frohberg
Life of this patent
Estimating the term…
Abstract
By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.
Claims29
A method, comprising:
- forming a first layer comprising a first dielectric material over a structure having lines and spaces, said first dielectric layer conformally covering said structure and said spaces having a first aspect ratio prior to forming said first dielectric layer;
- without forming or depositing an interposing spacer, layer, or partial layer therebetween, forming a second layer comprising a second dielectric material on the entirety of said first dielectric layer, said second layer partially filling said spaces, said partial filling of said spaces resulting in said spaces having a second aspect ratio less than said first aspect ratio;
- and
- forming a third layer comprising said second dielectric material above said second layer by a plasma enhanced chemical vapor deposition technique to enclose said structure.
A method of forming a dielectric interlayer between a device layer including closely spaced lines and a first metallization layer, wherein spaces between said closely spaced lines have a first aspect ratio, the method comprising:
- depositing an etch stop layer above said device layer;
- depositing a first layer of silicon dioxide above said etch stop layer and said device layer by one of a thermal CVD process based on TEOS and a high density plasma CVD process, wherein after depositing said first layer of silicon dioxide said spaces between said closely space lines have a second aspect ratio less than said first aspect ratio;
- depositing a second layer of silicon dioxide above said first layer by a plasma enhanced CVD process based on TEOS;
- and
- planarizing said second layer by CMP.
A method of forming a dielectric interlayer between a device layer including closely spaced lines and a first metallization layer, wherein spaces between said closely spaced lines have a first aspect ratio, the method comprising:
- depositing a first layer of silicon dioxide over said device layer by one of a thermal CVD process based on TEOS and a high density plasma CVD process, wherein after depositing said first layer of silicon dioxide over said device layer, said spaces between said closely space lines have a second aspect ratio less than said first aspect ratio;
- depositing an etch stop layer on said first layer;
- depositing a second layer of silicon dioxide above said etch stop layer by a plasma enhanced CVD process based on TEOS;
- and
- planarizing said second layer by CMP.
A method, comprising:
- forming a device layer comprising a plurality of closely spaced gate electrode structures above a semiconductor substrate, wherein spaces between each of said plurality of closely spaced gate electrode structures comprise a first aspect ratio, said first aspect ratio comprising a width;
- depositing a conformal etch stop layer above said device layer comprising said plurality of closely spaced gate electrode structures;
- depositing a first layer of a dielectric material above said conformal etch stop layer by one of a chemical vapor deposition technique at sub-atmospheric pressure based on TEOS and a high density plasma chemical vapor deposition process, wherein after depositing said first layer of said dielectric material, said spaces between said plurality of closely space gate electrode structures comprise a second aspect ratio, said second aspect ratio being less than said first aspect ratio;
- depositing a second layer of said dielectric material above said first layer of said dielectric material by a plasma enhanced chemical vapor deposition process based on TEOS;
- planarizing said second layer of said dielectric;
- and
- forming a metallization layer above said planarized second layer of said dielectric material.
A method, comprising:
- forming a device layer comprising a plurality of closely spaced gate electrode structures above a semiconductor substrate, wherein spaces between each of said plurality of closely spaced gate electrode structures comprise a first aspect ratio, said first aspect ratio comprising a width;
- depositing a first layer of a dielectric material above said device layer comprising said plurality of closely spaced gate electrode structures by one of a chemical vapor deposition technique at sub-atmospheric pressure based on TEOS and a high density plasma chemical vapor deposition process, wherein after depositing said first layer of said dielectric material, said spaces between said plurality of closely space gate electrode structures comprise a second aspect ratio, said second aspect ratio being less than said first aspect ratio;
- depositing an etch stop layer above said first layer of a dielectric material;
- depositing a second layer of said dielectric material above said etch stop layer by a plasma enhanced chemical vapor deposition process based on TEOS;
- planarizing said second layer of said dielectric material;
- and
- forming a metallization layer above said planarized second layer of said dielectric material.
Dependencies are inferred from the claim text.