US 8,772,127 B2 · Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Claims16

Dependent claims

A method for manufacturing a semiconductor device, comprising:

providing a silicon substrate having {100} crystal indices with a gate stack structure formed thereon;
forming a second isolation region within the silicon substrate wherein the second isolation region comprises a second dielectric layer;
forming an interlayer dielectric layer to cover a top surface of the silicon substrate;
forming a first trench in the interlayer dielectric layer and/or in the gate stack structure above the second isolation region, and the second dielectric layer is exposed at a bottom of the first trench, wherein the first trench has an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure;
and
filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile-stressed dielectric layer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/142,591Filed 27 Jan 2011

Priority

CN 2010 1 061257729 Dec 2010

Published

US 2012/0168881 A15 Jul 2012

Granted

8 Jul 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/0223
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
H10D 30/795
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in lateral device isolation regions, e.g. STI
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]

Semiconductor device and method for manufacturing the same

Life of this patent

Semiconductor device and method for manufacturing the same

Life of this patent

Abstract

Claims16