Combination FinFET and planar FET semiconductor device and methods of making such a device

A method of forming a device comprised of a plurality of fins and a plurality of trenches formed in a substantially un-doped layer of semiconducting material, the method comprising:

• forming a buffer layer comprised of at least carbon in a substrate;
• performing an epitaxial deposition process to form a substantially un-doped layer of epitaxial silicon above said buffer layer;
• identifying a top width of each of said plurality of fins and a depth of each of said plurality of trenches such that, during operation, said device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to said device;
• performing at least one process operation to define said plurality of trenches in said substantially un-doped layer of semiconducting material, wherein said trenches define said plurality of fins in said substantially un-doped layer of epitaxial silicon;
• forming a gate insulation layer on said plurality of fins and on a bottom of each of said trenches;
• and
• forming a gate electrode above said gate insulation layer.

A method of forming a combination device in a substantially un-doped layer of semiconducting material, wherein said combination device is comprised of a plurality of spaced-apart FinFET device portions, each of which are comprised of at least one fin, and a plurality of substantially planar FET device portions, wherein the method comprises:

• identifying a target threshold voltage for said combination device;
• identifying at least one of a target top width of each of said fins or a target thickness of said substantially planar FET device portions such that, during operation, said combination device is intended to exhibit said target threshold voltage;
• forming a plurality of trenches in said substantially un-doped layer of semiconducting material so as to define said plurality of fins and said substantially planar FET device portions, wherein each of said fins have a top width that is approximately equal to said target top width, and said substantially planar FET device portions have a thickness that is approximately equal to said target thickness;
• forming a gate insulation layer on said plurality of fins and on an upper surface of said substantially planar FET device portions;
• and
• forming a gate electrode above said gate insulation layer.

A method of forming a combination device in a substantially un-doped layer of semiconducting material, wherein said combination device is comprised of a plurality of spaced-apart FinFET device portions, each of which are comprised of at least one fin, and a plurality of substantially planar FET device portions, wherein the method comprises:

• identifying a target threshold voltage that is the same for said FinFET device portions and said substantially planar FET device portions;
• identifying a target top width of each of said fins such that, during operation, said FinFET device portions are intended to exhibit said target threshold voltage;
• identifying a target thickness of said substantially planar FET device portions such that, during operation, said planar FET portions are intended to exhibit said target threshold voltage;
• forming a plurality of trenches in said substantially un-doped layer of semiconducting material so as to define said plurality of fins and said substantially planar FET device portions, wherein each of said fins have a top width that is approximately equal to said target top width, and said substantially planar FET device portions have a thickness that is approximately equal to said target thickness;
• forming a gate insulation layer on said plurality of fins and on an upper surface of said substantially planar FET device portions;
• and
• forming a gate electrode above said gate insulation layer.