Low temperature implant scheme to improve BJT current gain

A process of forming an integrated circuit containing a pnp BJT and a p-channel metal oxide semiconductor (PMOS) transistor, comprising:

• forming a implant screen dielectric layer over a top surface of a silicon top region of a substrate of said integrated circuit, over an emitter region of said pnp BJT and source and drain regions of said PMOS transistor;
• forming an implant mask over said implant screen dielectric layer so as to expose said emitter region and said source and drain regions;
• bringing said substrate of said integrated circuit in contact with a substrate chuck;
• cooling said substrate chuck so that said substrate of said integrated circuit is cooled to a temperature of 5° C. or colder;
• and
• while said substrate is cooled to 5° C. or cooler, ion implanting p-type dopants concurrently into said emitter region and said source and drain regions, in which said p-type dopants and a dose of said p-type dopants are selected from the group consisting of
• boron at a dose of at least 1×1016 atoms/cm2,
• gallium at a dose of at least 7×1013 atoms/cm2,
• indium at a dose of at least 6×1013 atoms/cm2, and
• any combination thereof.