Chip package structure and manufacturing method thereof

A method of manufacturing a chip package structure, comprising the steps of:

• providing a metal layer having a first upper surface and a first lower surface;
• patterning the first upper surface of the metal layer to define a chip mounting portion and a plurality of lead portions, wherein the lead portions and the chip mounting portion have a gap therebetween;
• forming an insulating layer in the gap;
• patterning the first lower surface of the metal layer to remove a portion of the metal layer below the lead portions and below the insulating layer, so as to form a plurality of leads and a die pad, the die pad and the leads constituting a leadframe, wherein the die pad has the chip mounting portion and a periphery portion, the die pad has a second upper surface lying between the first upper surface and the first lower surface of the metal layer at the periphery portion, each of the leads has a suspending portion and a terminal portion, the lead has a second lower surface lying between the first upper surface and the first lower surface of the metal layer at the suspending portion, the suspending portion connects with the terminal portion and extends from the terminal portion toward the die pad, the insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad;
• mounting a chip on the chip mounting portion and electrically connecting the chip to the suspending portions through a plurality of bonding wires;
• and
• forming an encapsulant to cover the chip, the bonding wires, the insulating layer, and the leadframe.