Throughput-aware software pipelining for highly multi-threaded systems

A computer-implemented compiler system for throughput-aware software pipelining of an inner loop of a source code listing using a pipelining module of a computer-implemented compiler, the system comprising:

• a driver module, implemented in at least one processor such that the at least one processor is configured to identify an inner loop of a source code listing of a computer program for pipelining;
• a pipelining module, implemented in the at least one processor such that the at least one processor is configured to:
• identify an instruction of the inner loop;
• calculate a base latency for the instruction;
• define a loop latency as the base latency for the instruction according at least to a scalarity of an assumed multi-threaded execution environment;
• generate a proposed instruction schedule for the inner loop at least as a function of the loop latency in the pipelining module;
• and
• calculate whether the proposed instruction schedule meets a predetermined set of optimization criteria;
• and
• a multi-thread optimization module, implemented in the at least one processor such that the at least one processor is configured, while the proposed instruction schedule does not meet the predetermined set of optimization criteria, to iteratively perform steps comprising:
• reducing the loop latency in the pipelining module by reducing at least one of the scalarity or the base latency for the instruction;
• regenerating the proposed instruction schedule for the inner loop at least as a function of the reduced loop latency in the pipelining module;
• and
• calculating whether the regenerated proposed instruction schedule meets the predetermined set of optimization criteria.

A computer program product having a pipelining module for throughput-aware software pipelining of an inner loop of a source code listing, the computer program product residing on a non-transitory, processor-readable medium and having processor-readable instructions, which, when executed, cause a processor to perform steps comprising:

• identifying an instruction of the inner loop;
• calculating a base latency for the instruction;
• defining a loop latency in the pipelining module as the base latency for the instruction according at least to a scalarity of an assumed multi-threaded execution environment;
• generating a proposed instruction schedule for the inner loop at least as a function of the loop latency in the pipelining module;
• calculating whether the proposed instruction schedule meets a predetermined set of optimization criteria;
• while the proposed instruction schedule does not meet the predetermined set of optimization criteria, iteratively performing steps comprising:
• reducing the loop latency in the pipelining module by reducing at least one of the scalarity or the base latency for the instruction;
• regenerating the proposed instruction schedule for the inner loop at least as a function of the reduced loop latency in the pipelining module;
• and
• calculating whether the regenerated proposed instruction schedule meets the predetermined set of optimization criteria;
• and
• compiling the inner loop according to the proposed instruction schedule when the proposed instruction schedule meets the predetermined set of optimization criteria.