US 8,751,998 B2 · Method and system for partial reconfiguration simulation

Abstract

Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.

Claims20

Dependent claims

A method comprising:

in a computing system, simulating a device including a fixed logic region and a plurality of reconfigurable logic regions, the fixed logic region for performing fixed functionality and the plurality of reconfigurable logic regions reconfigurable for performing functionalities associated with a plurality of designs, wherein the plurality of designs includes a first design and a second design;
and
receiving a run-time parameter and reconfiguring at least one reconfigurable region of the plurality of reconfigurable logic regions from the first design to the second design in response to the run-time parameter while simulation of the device is running;
and
identifying at least one output signal that has a value corresponding to an indeterminate state after the reconfiguring of the at least one reconfigurable region and before a sub-system reset of the at least one reconfigurable logic region.

2 more elements

A system comprising:

a processor for simulating a device including a fixed logic region and a plurality of reconfigurable logic regions, the fixed logic region for performing fixed functionality and the plurality of reconfigurable logic regions reconfigurable and for performing functionalities associated with a plurality of designs, wherein the plurality of designs includes a first design and a second design;
and
an interface for receiving a run-time parameter and reconfiguring at least one reconfigurable region of the plurality of reconfigurable logic regions from the first design to the second design in response to the run-time parameter while simulation of the device is running;
and
identifying at least one output signal that has a value corresponding to an indeterminate state after the reconfiguring of the at least one reconfigurable region and before a sub-system reset of the at least one reconfigurable logic region.

2 more elements

A non-transitory computer readable storage medium comprising computer code embodied therein, the computer readable storage medium comprising:

computer code for simulating a device including a fixed logic region and a plurality of reconfigurable logic regions, the fixed logic region for performing fixed functionality and the plurality of reconfigurable logic regions reconfigurable and for performing functionalities associated with a plurality of designs, wherein the plurality of designs includes a first design and a second design;
and
computer code for receiving a run-time parameter and reconfiguring at least one reconfigurable region of the plurality of reconfigurable logic regions from the first design to the second design in response to the run-time parameter while simulation of the device is running;
and
identifying at least one output signal that has a value corresponding to an indeterminate state after the reconfiguring of the at least one reconfigurable region and before a sub-system reset of the at least one reconfigurable logic region.

2 more elements

Dependencies are inferred from the claim text.

Method and system for partial reconfiguration simulation

Life of this patent

Method and system for partial reconfiguration simulation

Life of this patent

Abstract

Claims20