Processing a fast speed grade circuit design for use on a slower speed grade integrated circuit

A system, comprising:

• a processor programmed to initiate executable operations comprising:
• receiving a first bitstream specifying a circuit design;
• wherein the circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit;
• determining a first parameter of the first bitstream;
• applying the first parameter to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design;
• performing a timing analysis upon the parameterized hardware netlist;
• and
• determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit;
• wherein the second speed grade is slower than the first speed grade.

A non-transitory computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform a method comprising:

• receiving a first bitstream specifying a circuit design;
• wherein the circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit;
• determining, using a processor, a first parameter of the first bitstream;
• applying the first parameter to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design;
• performing a timing analysis upon the parameterized hardware netlist;
• and
• determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit;
• wherein the second speed grade is slower than the first speed grade.