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US 8,751,996 B1Granted
Automatically routing nets according to parasitic constraint rules
AssigneePulsic Limited
InventorsJeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
Life of this patent
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Abstract
A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.
Claims20
A method comprising:
- providing an integrated circuit design having a plurality of source cells and sink cells to be routed using a plurality of nets;
- identifying a source cell and sink cell pair of the plurality as a critical signal path having a timing constraint;
- and
- using at least one electronic processor, automatically routing nets between the source cells and the sink cells, wherein parasitics of the integrated circuit design are taken into consideration during routing of a critical signal path net, the automatically routing nets comprises:
- estimating parasitics for a course of the critical signal path net;
- after estimating parasitics, generating a first segment of the critical signal path net;
- and
- using the estimated parasitics, determining a second segment of the critical signal path net.
5 more elements
A method comprising:
- providing an integrated circuit design having a plurality of source cells and sink cells to be routed using a plurality of nets;
- identifying a source cell and sink cell pair of the plurality as a critical signal path having a timing constraint;
- and
- using at least one electronic processor, automatically routing nets between the source cell and the sink cell pair comprising:
- estimating parasitics for a course of a critical signal path net, wherein the parasitics comprises resistance and capacitance values;
- after estimating parasitics, generating a first segment of the critical signal path net;
- and
- using the estimated parasitics, determining a second segment of the critical signal path net.
5 more elements
A method comprising:
- providing an integrated circuit design having a plurality of source cells and sink cells to be routed using a plurality of nets;
- identifying a source cell and sink cell pair of the plurality as a critical signal path having a timing constraint;
- and
- using at least one electronic processor, automatically routing nets between the source cell and the sink cell pair comprising:
- estimating parasitics for a course of a critical signal path net, wherein the parasitics comprise resistance and capacitance values;
- dividing the layout into bins;
- estimating parasitics for each bin;
- after estimating parasitics, generating a first segment of the critical signal path net;
- using the estimated parasitics, determining a second segment of the critical signal path net;
- providing a timing constraint rule for the critical signal path net;
- evaluating whether the critical signal path net satisfies the timing constraint rule;
- and
- if the timing constraint rule is not satisfied, altering the routing of the critical signal path net.
10 more elements
Dependencies are inferred from the claim text.