Method and apparatus for automatic relative placement rule generation

A non-transitory computer readable medium encoded with executable instructions for circuit design with a computer system, comprising:

• computer executable instructions generating with the computer system a placed, routed, and optimized circuit design, including:
• computer executable instructions guiding coarse placement of the circuit design according to rules created specifically and automatically for a set of circuit elements in the circuit design, at least one of the rules specified at a register transfer language-level in response to a register transfer language-level construct in the circuit design, the rules specifying positioning of each circuit element of the set of circuit elements in the circuit design relative to other circuit elements of the set of circuit elements in the circuit design;
• and
• computer executable instructions completing synthesis placement, routing, and optimization of the circuit design according to the rules,
• wherein the register transfer language-level construct includes at least one of:
• (i) a plurality of register banks that are part of a pipelined datapath, and the rules specify spaces between register banks of the pipelined datapath, and the spaces are sufficient for combinational logic coupling together different register banks of the pipelined datapath;
• and
• (ii) a multiplexer having a bit width of M and a number of inputs per bit of N, and the multiplexer has a rectangle shape with a width and a height such that M is equal to a product of the width times the height.

A computer system configured for circuit design, including:

• a processor and memory generating a placed, routed, and optimized circuit design,
• the processor and memory guiding coarse placement of the circuit design according to rules created specifically and automatically for a set of circuit elements in the circuit design, at least one of the rules specified at a register transfer language-level in response to a register transfer language-level construct in the circuit design, the rules specifying positioning of each circuit element of the set of circuit elements in the circuit design relative to other circuit elements of the set of circuit elements in the circuit design;
• and
• the processor and memory completing synthesis placement, routing, and optimization of the circuit design according to the rules,
• wherein the register transfer language-level construct includes at least one of:
• (i) a plurality of register banks that are part of a pipelined datapath, and the rules specify spaces between register banks of the pipelined datapath, and the spaces are sufficient for combinational logic coupling together different register banks of the pipelined datapath;
• and
• (ii) a multiplexer having a bit width of M and a number of inputs per bit of N, and the multiplexer has a rectangle shape with a width and a height such that M is equal to a product of the width times the height.