Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination

A computer system comprising:

• a storage device comprising program instructions;
• and
• a processor configured to execute the program instructions to perform a method comprising:
• facilitating hierarchy-based layout versus schematic verification, the facilitating comprising:
• obtaining a hierarchical layout netlist for a circuit design, wherein the hierarchical layout netlist groups arrayed devices of the circuit design into a plurality of blocks repeated at a top level of a hierarchy of the hierarchical layout netlist, wherein each connection of the hierarchical layout netlist extending from a component of a block is made to a top level pad of the circuit design, and wherein obtaining the hierarchical layout netlist comprises:
• obtaining an existing circuit layout design for the circuit;
• and
• adjusting the obtained existing circuit layout to obtain an adjusted layout hierarchy in which arrays of active devices are grouped into separate blocks having connections to top level pads of the circuit design, wherein each connection of the adjusted layout hierarchy extending from a component of a block of the separate blocks is made to a pad of the circuit design, and wherein the obtained hierarchical layout netlist is extracted from the adjusted layout hierarchy;
• generating a modified hierarchical layout netlist defining active devices and connections thereof to the top level pads of the circuit design, the generating comprising selectively removing extraneous devices from the obtained hierarchical layout netlist;
• and
• verifying the modified hierarchical layout netlist against an input schematic netlist defining the active devices of the circuit design and connections thereof to the top level pads of the circuit design.

A computer program product comprising:

• a tangible storage medium storing program instructions readable by a processor for execution to perform a method comprising:
• facilitating hierarchy-based layout versus schematic verification, the facilitating comprising:
• obtaining a hierarchical layout netlist for a circuit design, wherein the hierarchical layout netlist groups arrayed devices of the circuit design into a plurality of blocks repeated at a top level of a hierarchy of the hierarchical layout netlist, wherein each connection of the hierarchical layout netlist extending from a component of a block is made to a top level pad of the circuit design, and wherein obtaining the hierarchical layout netlist comprises:
• obtaining an existing circuit layout design for the circuit;
• and
• adjusting the obtained existing circuit layout to obtain an adjusted layout hierarchy in which arrays of active devices are grouped into separate blocks having connections to top level pads of the circuit design, wherein each connection of the adjusted layout hierarchy extending from a component of a block of the separate blocks is made to a pad of the circuit design, and wherein the obtained hierarchical layout netlist is extracted from the adjusted layout hierarchy;
• generating a modified hierarchical layout netlist defining active devices and connections thereof to the top level pads of the circuit design, the generating comprising selectively removing extraneous devices from the obtained hierarchical layout netlist;
• and
• verifying the modified hierarchical layout netlist against an input schematic netlist defining the active devices of the circuit design and connections thereof to the top level pads of the circuit design.