Method for design partitioning at the behavioral circuit design level

An apparatus for performing design partitioning at the behavioral circuit design level comprising:

• an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design;
• an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design;
• a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements to produce a flattened circuit design;
• a partition specification reader module that defines selected paths within the circuit design into a partition specification;
• wherein the expression graph module traces selected paths from inputs to outputs according to the partition specification;
• a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification;
• a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the hardware descriptive language of the circuit design;
• and
• an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.