Implementing dual speed level shifter with automatic mode control

A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing a dual speed level shifter with automatic mode control, said circuit comprising:
• a low speed level shifter and a high speed level shifter, each receiving an incoming signal to be level shifted and each having an enable input;
• a first counter receiving the incoming signal to be level shifted;
• a second counter receiving a reference signal;
• said first counter and said second counter having an equal size;
• each of said first counter and said second counter having a respective overflow output;
• and
• a set reset latch (SR) latch receiving a respective set input and reset input of said respective overflow outputs for automatically selecting a low speed mode enabling the low speed level shifter or a high speed mode enabling the high speed level shifter, the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.