US 8,751,975 B2Granted

RC corner solutions for double patterning technology

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsKe-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng

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Abstract

A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.

Claims13

Dependent claims

A method comprising:

determining model parameters for forming an integrated circuit;
and
generating a techfile using the model parameters, wherein the generating the techfile is performed using a computer, and wherein the techfile comprises at least two of a C_worst table, a C_best table, and a C_nominal table, and wherein:
the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other;
the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other;
and
the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other, wherein the techfile is embodied on a tangible non-transitory storage medium, wherein the step of generating the techfile comprises:
determining a maximum shift of a first lithography mask relative to a second lithography mask, wherein the first and the second lithography masks are comprised in a double patterning mask set;
selecting a shift magnitude smaller than the maximum shift, wherein the shift magnitude represents a shift of a first net in the first lithography mask relative to second nets in the second lithography mask;
calculating coupling capacitance values between the first net and each of the second nets;
calculating a total capacitance of the capacitance values;
repeating the steps of selecting, calculating the coupling capacitance values, and calculating the total capacitance, wherein in each cycle of the repeating, an additional shift magnitude different from the shift magnitude is selected, and an additional total parasitic capacitance is calculated;
selecting a greatest capacitance from the total parasitic capacitance and the additional total parasitic capacitance;
and
selecting a smallest capacitance from the total parasitic capacitance and the additional total parasitic capacitance;
and
converting the greatest capacitance and the smallest capacitance into an equivalent k_worst value and a k_best value, respectively, wherein the k_worst value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to increase to the greatest capacitance when the first lithography mask shift relative to the second lithography mask, and wherein the k_best value represents a k value that causes a parasitic capacitance between the first net and one of the second nets to reduce to the smallest capacitance when the first lithography mask shift relative to the second lithography mask.

14 more elements

A method comprising:

analyzing polygons in a layout of an integrated circuit, wherein the layout is embodied on a tangible non-transitory computer-readable medium;
partitioning the polygons into nets, wherein the partitioning the polygons is performed using a computer;
finding at least one parasitic capacitance of each of the nets from a techfile, wherein the techfile comprises at least two of a C_worst table, a C_best table, and a C_nominal table, and wherein:
the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other;
the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other;
and
the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other, wherein during the step of finding, a width and a spacing of the each of the nets are used to index into at least one of the C_worst table, the C_best table, and the C_nominal table, wherein finding the at least one parasitic capacitance comprises, for at least one of the each of the nets, finding a C_worst value form the C_worst table, finding a C_best value form the C_best table, and finding a C_nominal value form the C_nominal table;
reading mask designators of the nets from the layout;
and
for portions of the nets (same-mask nets) that are marked with the same one of the mask designators, replacing parasitic capacitance values of the same-mask nets with nominal capacitances found from the C_nominal table.

7 more elements

A method comprising:

analyzing polygons in a layout of an integrated circuit, wherein the layout is embodied on a tangible non-transitory computer-readable medium, and wherein the analyzing the polygons is performed using a computer;
partitioning the polygons into nets;
finding at least two of a worst capacitance, a best capacitance, and a nominal capacitance for each of the nets from a C_worst table, a C_best table, and a C_nominal table, respectively, wherein the step of finding comprises indexing into the C_worst table, the C_best table, and the C_nominal table using widths and spacings of the nets as indexes, wherein:
the worst capacitance is the capacitance between the net and neighboring nets when lithography masks comprising patterns of the net shifts relative to each other;
the best capacitance is a capacitance between the net and the neighboring nets when the lithography masks comprising the patterns of the net shifts relative to each other;
the nominal capacitance is a capacitance between the net and the neighboring nets when the lithography masks comprising the patterns of the net do not shift relative to each other;
the C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other;
the C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other;
and
the C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other;
reading colors of the nets from the layout;
and
replacing parasitic capacitance values of portions of the nets that have a same color with nominal capacitances found from the C_nominal table.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/479,076Filed 23 May 2012 · us provisional application
Priority: 13 Apr 2012
Published: US 2013/0275927 A117 Oct 2013
Granted: 10 Jun 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification2 codes

G06F 30/39
Circuit design: circuit design at the physical level
G06F
Computing and data processing

Family

Application61/623,939Us provisional application · filed 13 Apr 2012
US 2013/0275927 A1Pre-grant publication · published 17 Oct 2013
US 8,751,975 B2This patent

From the US filing history. Foreign family members aren’t listed.

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