Systems and methods for reduced power multi-layer data decoding
AssigneeLSI Corporation
InventorsZongwang Li, Lei Chen, Chung-Li Wang
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Abstract
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data encoder circuit. The data encoder circuit is operable to apply an encoding algorithm to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set. The last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix.
Claims20
A data processing system, the data processing system comprising:
- a data encoder circuit operable to apply an encoding algorithm to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set, wherein the last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix.
A method for data processing, the method comprising:
- applying an encoding algorithm by a data encoder circuit to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set, wherein the last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix.
A storage device, the storage device comprising:
- a data encoder circuit operable to apply an encoding algorithm to an input data set in accordance with a multi-layer code structure including a first row and a last row to yield an encoded data set, wherein the last row of the multi-layer code structure represented in the encoded data set conforms to an identity matrix;
- a storage medium operable receive a data set corresponding to the encoded data set;
- a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to the encoded data set;
- a read channel circuit including:
- an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples;
- an equalizer circuit operable to equalize the digital samples to yield detector data set corresponding to the encoded data set;
- a data detector circuit operable to apply a data detection algorithm to the data set to yield a detected output;
- a data decoder circuit operable to:
- add a second decoded output from the decoder input to yield a first summed output;
- shift the summed output to conform with the identity matrix to yield a shifted output;
- subtract a third decoded output from the shifted output to yield a second summed output;
- and wherein the first summed output is provided unshifted as an output codeword.
Dependencies are inferred from the claim text.