Layered low density parity check decoder
AssigneeMarvell International Ltd.
InventorsNedeljko Varnica, Panu Chaichanavong, Heng Tang
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AssigneeMarvell International Ltd.
InventorsNedeljko Varnica, Panu Chaichanavong, Heng Tang
Estimating the term…
Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. According to one embodiment, an apparatus includes a plurality of hardware layers, where a hardware layer is configured to compute a syndrome value from one or more bit values in the codeword. The apparatus includes a plurality of physical memories configured to store a plurality of syndrome values, where a physical memory is configured to store syndrome values computed by one or more hardware layers. The apparatus includes circuitry configured to simultaneously store a syndrome value computed by a hardware layer in physical memories associated with a bit in the codeword. The apparatus includes a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on values stored in the plurality of physical memories.
A layered, low density parity check (LDPC) decoder apparatus configured to decode a codeword, comprising:
A method comprising:
A device, comprising:
Dependencies are inferred from the claim text.