Memory with on-chip error correction

An apparatus comprising:

• digital circuitry responsive to digital information;
• analog circuitry coupled to the digital circuitry and responsive to analog information;
• a memory device, coupled to the digital circuitry, and having a magnetic memory unit made of a plurality of memory cells organized in an array of rows and columns, rows comprising of plurality of pages that store codewords, the memory device configured to correct errors during write and read operations to a memory array and comprising:
• a data latch responsive to an addressed page of data from a memory array and operative to generate a data latch output;
• a codeword corrector responsive to the data latch output, the data latch output including a first codeword, the codeword corrector operative to correct errors, if any, in the first codeword and generate a codeword corrector output including a corrected first codeword;
• a data buffer responsive to the codeword corrector output and a first user data associated with the addressed page provided by a user of the memory device and operative to generate a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output;
• a codeword encoder responsive to the data buffer output and operative to encode the first codeword output to generate an encoded first codeword output included in a codeword encoder output;
• and
• a write buffer responsive to the codeword encoder output and configured to save the received codeword encoder output and to provide a write data to the memory array,
• wherein providing the write data to the memory array is performed while receiving a second user data, the second user data having a second codeword associated therewith, and correcting the second codeword.