Semiconductor memory device and decoding method

A semiconductor memory device comprising:

• a semiconductor memory unit configured to store encoded data encoded with an LDPC code;
• and
• a decoding unit configured to decode the encoded data using a Min-Sum algorithm or a Modified-Min-Sum algorithm,
• wherein the decoding unit performs serial decoding by repeatedly performing iterative processing which includes row processing and column processing and thereby updating a posterior likelihood ratio for each row of a parity check matrix, and uses the posterior likelihood ratio as it is for a column element likelihood ratio when an absolute value of the posterior likelihood ratio is equal to or larger than a threshold and uses the column element likelihood ratio as it is for the posterior likelihood ratio when an absolute value of the column element likelihood ratio is equal to or larger than the threshold, and
• if the decoding does not succeed even after a predetermined first cycle count of the iterative processing is performed or if a number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”