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US 8,751,887 B2Granted
Enable gating clock, shift, capture, and update to first gating
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.
Claims2
An integrated circuit comprising:
- A. a clock lead, a shift lead, a capture lead, an update lead, a select lead, a serial data in lead, and a serial data out lead;
- B. an instruction register having inputs coupled to the clock lead, the shift lead, the capture lead, the update lead, and the serial data in lead, and having a serial data out output and control outputs;
- C. an internal scan register having inputs coupled to the clock lead, the shift lead, the capture lead, the update lead, and the serial data in lead, and having a serial data out output and a control input coupled to a control output of the instruction register;
- D. a boundary scan register having inputs coupled to the clock lead, the shift lead, the capture lead, the update lead, and the serial data in lead, and having a serial data out output and a control input coupled to a control output of the instruction register;
- E. a bypass register having inputs coupled to the clock lead, the shift lead, the capture lead, the update lead, and the serial data in lead, and having a serial data out output and a control input coupled to a control output of the instruction register;
- F. first multiplexer circuitry having inputs connected to the serial data out outputs of the internal scan register, the boundary scan register, and the bypass register and having a serial data out output;
- G. second multiplexer circuitry having inputs connected to the serial data out output of the first multiplexer circuitry and the instruction register and having a serial data out output coupled to the serial data out lead;
- H. first gating circuitry coupled to the select lead and coupling the clock lead, the shift lead, the capture lead, and the update lead, to the instruction register, the internal scan register, the boundary scan register, and the bypass register;
- I. an enable lead;
- and
- J. second gating circuitry connected to the enable lead and coupling at least one of the clock lead, the shift lead, the capture lead, and the update lead, to the first gating circuitry.
8 more elements
Dependencies are inferred from the claim text.