Scan test circuitry with selectable transition launch mode

Abstract

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises transition launch mode selection circuitry configured to provide independent selection between multiple transition launch modes for each of a plurality of clock domains of the integrated circuit. The multiple transition launch modes may include, for example, at least a launch-on-shift mode and a launch-on-capture mode. These transition launch modes provide different manners of launching a given signal transition via at least one of the scan cells in a corresponding one of the clock domains. The transition launch mode selection circuitry may be configured to generate from a common shift enable signal multiple independently controllable shift enable signals for respective ones of the clock domains of the integrated circuit.

Dependencies are inferred from the claim text.