Apparatus and method to measure timing margin in clock and data recovery system utilizing a jitter stressor
AssigneeBroadcom Corporation
InventorsMagesh Valliappan, Lin Zheng, Bruce Howard Conway
Life of this patent
Estimating the term…
Abstract
A method and a system for accurately calculating the timing margin in a clock and data recovery system (CDR) is provided that utilizes a singular path environment of hardware. The method entails adding an amount of jitter within the CDR to change the receiver phase. The amount of jitter is incrementally increased until a threshold level of bit errors occur. Based on the amount of jitter needed to cause the threshold level of bit errors, timing margin can be calculated.
Claims22
An apparatus for calculating timing margin in a clock and data recovery (CDR) system, comprising:
- a first data latch configured to sample a digital signal in accordance with a sampling clock signal to provide an estimated digital sequence;
- a second data latch configured to identify edge transitions of the digital signal in accordance with the sampling clock signal to provide an edge sequence;
- a phase detector configured to compare the estimated digital sequence and the edge sequence to provide an error signal;
- a summer configured to combine the error signal and a jitter signal to provide a sampling clock signal phase control;
- a jitter signal stressor configured to provide the jitter signal in response to a jitter signal stressor control;
- a phase controller configured to adjust a phase of the sampling clock signal in response to the sampling clock signal phase control;
- and
- an evaluator module configured to compare the estimated digital sequence with the digital signal and to cause an increase in the jitter signal until a number of bit errors generated by the first data latch is greater than or equal to a threshold value.
A method for calculating timing margin in a clock and data recovery (CDR) system, comprising:
- sampling a digital signal in accordance with a sampling clock signal to provide an estimated digital sequence;
- identifying edge transitions of the digital signal in accordance with the sampling clock signal to provide an edge sequence;
- comparing the estimated digital sequence and the edge sequence to provide an error signal;
- combining the error signal and a jitter signal to provide a sampling clock signal phase control;
- adjusting a phase of the sampling clock signal in response to the sampling clock signal phase control;
- comparing the estimated digital sequence and the digital sequence to determine a number of bit errors;
- and
- increasing the jitter signal until the number of bit errors is greater than or equal to a threshold value.
Dependencies are inferred from the claim text.