US 8,751,853 B2 · Quad-data rate controller and implementing method thereof

Abstract

A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in “read data path calibrating state”; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. The present invention has a shorter delay and does not need any programmable delay element, and is easy to implement.

Claims11

Dependent claims

A Quad-Data Rate (QDR) controller, comprising:

an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module;
the arbiter is configured to arbitrate commands and data according to a state of the control state machine;
the control state machine is configured to manage a state of a controller and provide state basis for the arbiter to arbitrate the commands and the data;
the read data sampling clock generating module is configured to generate read data sampling clocks with a same source, a same frequency and different phases;
the read data path calibrating module is configured to determine, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data respectively when the read data path module reads data by reading training words when the control state machine is in “read data path calibrating state”;
the read data path module is configured to synchronize positive edge read data and negative edge read data that are in a non-system clock domain to a system clock domain according to the sampling clocks determined by the read data path calibrating module.

3 more elements

A method for implementing a Quad-Data Rate (QDR) controller, comprising:

sampling read data using 4 clocks with a same source and a same frequency and different phases in a QDR controller;
determining a sampling clock for the read data according to a result of sampling read data of each clock in the 4 clocks when a control state machine of the QDR controller is in “read data path calibrating state”;
synchronizing the read data to a system clock domain according to the determined sampling clock.

Dependencies are inferred from the claim text.

Quad-data rate controller and implementing method thereof

Life of this patent

Quad-data rate controller and implementing method thereof

Life of this patent

Abstract

Claims11