Programmable mechanism for delayed synchronous data reception

An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:

• a first microprocessor, comprising:
• a Joint Test Action Group (JTAG) interface, configured to receive control information over a standard JTAG bus, wherein said control information indicates first amount to delay a data bit signal relative to a synchronous data strobe signal associated with a data group;
• a synchronous bus optimizer, configured to receive said control information, and configured to develop a value on a first ratio bus that indicates said first amount;
• and
• a first delay-locked loop (DLL), coupled to said first ratio bus, configured generate a delayed data bit signal, wherein said first DLL adds said first amount of delay to said data bit signal to generate said delayed data bit signal;
• and
• a second microprocessor, coupled to said first microprocessor, said second microprocessor comprising:
• a core clocks generator, coupled to a second ratio bus, configured to advance a data strobe clock by a second amount, said core clocks generator comprising:
• a phase locked loop (PLL), comprising:
• PLL forward elements, configured to receive a bus clock signal, and configured to generate said data strobe clock signal at a frequency multiple of said bus clock signal;
• a second delay-locked loop (DLL), configured to receive said data strobe clock signal and said second ratio bus, and configured to generate an output that comprises said data strobe clock signal delayed by said second amount;
• and
• a frequency divider, configured to receive said output, and configured to generate a delayed reference signal to enable said PLL forward elements to align said output in phase with said bus clock signal, thereby causing said data strobe clock signal to be advanced by said second amount;
• and
• a synchronous strobe driver, configured to receive said data strobe clock signal, and configured to employ said data strobe clock signal to generate said synchronous data strobe signal, wherein said synchronous data strobe signal, when enabled, is advanced also by said second amount.

A method for compensating for misalignment on a synchronous data bus, the method comprising:

• via a Joint Test Action Group (JTAG) interface disposed within a receiving device, receiving control information over a standard JTAG bus, wherein the control information indicates a first amount to delay a data bit signal relative to a synchronous data strobe signal associated with a data group;
• based upon the control information, developing a first value on a first ratio bus that indicates the first amount;
• and
• first coupling a first delay-locked loop (DLL) disposed within the receiving device to the first ratio bus, and first configuring the first DLL generate a delayed data bit signal, wherein the first DLL adds the first amount of delay to the data bit signal to generate the delayed data bit signal;
• via a transmitting device that is coupled to the receiving device, coupling a second ratio bus to a core clocks generator, and advancing a data strobe clock by a second amount, the core clocks generator comprising:
• a phase locked loop (PLL), comprising:
• PLL forward elements, configured to receive a bus clock signal, and configured to generate the data strobe clock signal at a frequency multiple of said bus clock signal;
• a second delay-locked loop (DLL), configured to receive the data strobe clock signal and the second ratio bus, and configured to generate an output that comprises the data strobe clock signal delayed by the second amount;
• and
• a frequency divider, configured to receive the output, and configured to generate a delayed reference signal that is equal in frequency to the bus clock signal to enable the PLL forward elements to align the output in phase with the bus clock signal, thereby causing the data strobe clock signal to be advanced by the second amount;
• and
• first employing a synchronous strobe driver to receive the data strobe clock signal, and second employing the data strobe clock signal to generate the synchronous data strobe signal, wherein the synchronous data strobe signal, when enabled, is advanced also by the second amount.