Memory address translation-based data encryption/compression

A circuit arrangement, comprising:

• a multi-core processor including a plurality of processing cores;
• and
• a memory address translation data structure disposed in a first processing core among the plurality of processing cores, the memory address translation data structure configured to store address translation data for a memory page, wherein the memory address translation data structure is further configured to store an encryption-related page attribute for the memory page, wherein the encryption-related page attribute comprises a level attribute that identifies at least one level of a multi-level memory architecture within which the memory page is encrypted;
• wherein the multi-core processor is configured to, in response to a memory access request initiated by a thread in the first processing core and associated with the memory page, selectively stream secure data from the memory page through an encryption engine to perform an encryption operation on the secure data based upon whether the memory page associated with the memory access request is encrypted, wherein the memory access request comprises a first memory access request associated with a first process executed by the processing core, and wherein the first processing core is configured to, in response to a second memory access request associated with a second process that is not authorized to access the memory page, determine whether the memory page is encrypted, and when the memory page is encrypted, indicate that the page is encrypted when asserting a software exception.

A method of accessing data in a data processing system, the method comprising:

• in response to a memory access request initiated by a thread in a processing core, accessing a memory address translation data structure to perform a memory address translation for the memory access request;
• accessing an encryption-related page attribute in the memory address translation data structure to determine whether the memory page associated with the memory access request is encrypted;
• and
• selectively streaming secure data in the memory page through an encryption engine to perform an encryption operation on the secure data based upon whether the memory page associated with the memory access request is determined to be encrypted;
• wherein the memory access request comprises a first memory access request associated with a first process executed by the processing core, the method further comprising:
• in response to a second memory access request associated with a second process that is not authorized to access the memory page, determining whether the memory page is encrypted, and when the memory page is encrypted if so, performing a system shutdown.

A circuit arrangement, comprising:

• a multi-core processor including a plurality of processing cores;
• and
• a memory address translation data structure disposed in a first processing core among the plurality of processing cores, the memory address translation data structure configured to store address translation data for a memory page, wherein the memory address translation data structure is further configured to store an encryption-related page attribute for the memory page;
• wherein the multi-core processor is configured to, in response to a memory access request initiated by a thread in the first processing core and associated with the memory page, selectively stream secure data from the memory page through an encryption engine to perform an encryption operation on the secure data based upon whether the memory page associated with the memory access request is encrypted, wherein the memory access request comprises a first memory access request associated with a first process executed by the processing core, and wherein the first processing core is configured to, in response to a second memory access request associated with a second process that is not authorized to access the memory page, determine whether the memory page is encrypted, and when the memory page is encrypted, perform a system shutdown.