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US 8,751,754 B2Granted
Memory systems and methods for controlling the timing of receiving read data
AssigneeMicron Technology, Inc.
InventorsPaul A. LaBerge, James B. Johnson
Life of this patent
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Abstract
Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.
Claims20
An apparatus comprising:
- a plurality of memory devices, each memory device of the plurality of memory devices configured to capture a respective read command responsive, at least in part, to an array access signal and to provide respective read data corresponding to the respective read command responsive, at least in part, to a respective output control signal;
- and
- a controller operating according to a clock signal and configured to provide the array access signal to the plurality of memory devices and provide the respective output control signal for each of the plurality of memory devices responsive, at least in part, to providing a first read command to a first memory device of the plurality of memory devices and to providing a second read command to a second memory device of the plurality of memory devices, the controller configured to delay a time when read data corresponding to the second read command is provided by a delay less than one period of the clock signal.
An apparatus, comprising:
- a memory device configured to receive a read command and an array access signal, the memory device further configured to capture the read command responsive to the array access signal,
- wherein the array access signal includes a pulse having a rising edge and a falling edge, the memory device configured to capture the read command on the rising edge of the pulse, and the memory device configured to delay the read command until the falling edge of the pulse.
A method, comprising:
- receiving a read command and an array access signal from an interface;
- capturing the read command responsive, at least in part, to a rising edge of the array access signal;
- delaying the read command until a falling edge of the array access signal;
- generating a plurality of control signals to access read data associated with the read command in a memory array;
- and
- providing the read data to the interface.
3 more elements
Dependencies are inferred from the claim text.