Method and apparatus for minimizing cache conflict misses

A computer readable device having a computer program product for minimizing cache conflict misses, said computer readable device comprising:

• computer program code for providing a translation table having a plurality of entries, wherein each entry includes a page number field and a hash value field, wherein said translation table facilitates the translation of a virtual address to a real address during a cache access;
• computer program code for generating by a processor a hash value from a first group of bits within a virtual address;
• computer program code for storing said hash value in said hash value field of an entry within said translation table;
• and
• computer program code for, in response to a match on said entry within said translation table during a cache access, retrieving by said processor said hash value of said matched entry from said translation table, and concatenating by said processor said hash value with a second group of bits within said virtual address to form a set of indexing bits to index into a cache set.

An apparatus for minimizing cache conflict misses, said apparatus comprising:

• a hash function module for generating a hash value from a first group of bits within a virtual address;
• a translation table having a plurality of entries, wherein each entry includes a page number field and a hash value field, wherein said translation table facilitates the translation of a virtual address to a real address during a cache access, wherein said hash value is stored in said hash value field of an entry within said translation table;
• means for, in response to a match on said entry within said translation table during a cache access, retrieving said hash value of said matched entry from said translation table;
• and
• a combine function module for concatenating said hash value with a second group of bits within said virtual address to form a set of indexing bits to index into a cache set.