Hybrid memory management

An electronic system, comprising:

• a processor having a standard interface;
• a memory device coupled to the processor at least in part through the standard interface, the memory device comprising:
• a first array of memory cells of a first type;
• a second array of memory cells of a second type different from the first type;
• and
• control circuitry configured to store data determined by the control circuitry to be stored in the first array of memory cells of the first type and to store data determined by the control circuitry to be stored in the second array of memory cells of the second type,
• wherein the processor is adapted to instruct the control circuitry how to determine, based on the nature of the data, whether to store data in the first array of memory cells or the second array of memory cells, and wherein the control circuitry is further configured to output a size of the first array of memory cells and a size of the second array of memory cells in response to a request by the processor.

An electronic system, comprising:

• a processor having a standard interface;
• a memory device coupled to the processor at least in part through the standard interface, the memory device comprising:
• a first array of memory cells of a first type;
• a second array of memory cells of a second type different from the first type;
• and
• control circuitry configured to store data determined by the control circuitry to be stored in the first array of memory cells of the first type and to store data determined by the control circuitry to be stored in the second array of memory cells of the second type,
• wherein the processor is adapted to instruct the control circuitry how to determine, based on the nature of the data, whether to store data in the first array of memory cells or the second array of memory cells;
• and
• wherein the control circuitry is further configured to determine a nature of data to be associated with a logical location in memory based on information provided by the processor and at least partially based on the nature, to store the data in one of the first array of memory cells and the second array of memory cells and to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.

An electronic system comprising:

• a processor having a standard interface;
• a memory device coupled to the processor at least in part through the standard interface, the memory device comprising:
• a first array of memory cells of a first type;
• a second array of memory cells of a second type different from the first type;
• and
• control circuitry configured to store data determined by the control circuitry to be stored in the first array of memory cells of the first type and to store data determined by the control circuitry to be stored in the second array of memory cells of the second type,
• wherein the processor is adapted to instruct the control circuitry how to determine, based on the nature of the data, whether to store data in the first array of memory cells or the second array of memory cells;
• and
• wherein the control circuitry is configured to determine, based on information from the processor, a nature of data to be associated with a logical location in memory and, at least partially based on the nature, to store the data in one of the first array of memory cells and the second array of memory cells;
• and
• wherein the control circuitry is further configured to output from the memory device a size of the first array of memory cells and a size of the second array of memory cells in response to a request by the processor coupled to the memory device.

An electronic system having a processor in communication with a non-volatile memory device through a standard interface, the non-volatile memory device having physical storage locations associated with logical addresses, and wherein the logical addresses are associated with data, the memory device comprising:

• a first array of memory cells each memory cell having a first density;
• a second array of memory cells each memory cell having a second density;
• and
• a controller, wherein the controller is configured by the processor to selectively perform a write operation on the first array of memory cells or on the second array of memory cells and to assign the logical addresses to the physical storage locations based at least partially on a number of write operations performed on each logical address, and to re-assign logical addresses to the first array of memory cells if the number of write operations exceeds a threshold value and wherein the control circuitry is further configured by the processor to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.

An electronic system comprising:

• a processor that generates memory device control signals;
• and
• a memory device, coupled to the processor via a standard interface and configured to receive the memory device control signals, the memory device comprising:
• a first array of memory cells each memory cell having a first density;
• a second array of memory cells each memory cell having a second density;
• and
• control circuitry, wherein the control circuitry is configured to store data in the first array of memory cells or the second array of memory cells based on interpreting a tracked history of received write operations issued to logical addresses of said data and wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.

An electronic system comprising:

• a processor that generates memory device control signals;
• and
• a memory device, coupled to the processor through a standard interface and configured to receive the memory device control signals, the memory device comprising:
• a first array of memory cells each memory cell having a first density;
• a second array of memory cells each memory cell having a second density;
• and
• control circuitry, wherein the control circuitry is configured to store data in the first array of memory cells or the second array of memory cells based on interpreting a tracked history of received write operations issued to logical addresses of said data;
• and
• wherein the processor instructs the control circuitry to store data in the first array of memory cells or the second array of memory cells based at least in part on if a logical address associated with the data is accessed during a boot load operation performed by the processor.

A non-volatile memory device having physical storage locations associated with logical addresses, and wherein the logical addresses are associated with data, the memory device comprising:

• a first array of memory cell each memory cell having a first density;
• a second array of memory cells each memory cell having a second density;
• and
• control circuitry configured to selectively perform a read operation on the first array of memory cells or the second array of memory cells and to determine, based on the nature of the data, if the read data is to be stored in the first array of memory cells of the first density or stored in the second array of memory cells of the second density wherein the control circuitry assigns logical addresses to the physical storage locations based at least partially on a number of read operations performed on each logical address, and to re-assign logical addresses to the first array of memory cells if the number of read operations exceeds a threshold value and wherein the control circuitry is further configured to maintain at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.