Flash memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKui-Yon Mun, Jongkeun Ahn
Life of this patent
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Abstract
A method of controlling a memory, determining whether data access is random; generating a first random sequence (RS) data based on a first seed if data access is not random (column offset=0); mixing the first RS data with data read from the memory or data to be written to the memory; generating a second seed from a first seed if data access is random (column offset not=0); generating a second RS data based on the second seed; and mixing the second RS data with data read from the memory or data to be written to the memory.
Claims44
A method of controlling a memory, comprising:
- determining whether data access is random;
- generating a first random sequence (RS) data based on a first seed if data access is not random;
- mixing the first RS data with data read from the memory or data to be written to the memory;
- generating a second seed from the first seed if data access is random;
- generating a second RS data based on the second seed;
- and
- mixing the second RS data with data read from the memory or data to be written to the memory.
A method of controlling a memory, comprising:
- receiving an offset address value N, N being a column portion of an access address;
- generating M random sequence (RS) data prior to derandomizing first read data based on the access address, wherein the maximum value of M is N;
- and
- derandomizing the first read data by mixing with an Nth RS data.
A method of controlling a memory, comprising:
- receiving an offset value N, N being a column portion of an access address;
- generating M random sequence data prior to derandomizing first read data based on the access address, wherein M is a range from 1 to less than the end of the column portion of the access address;
- and
- derandomizing the first read data using an Nth RS data.
A method of controlling a memory, comprising:
- receiving an column offset value N;
- generating at least one random sequence (RS) data based on a start seed until a count increased from a predetermined value reaches N;
- determining one of said at least one RS data as an initial RS data;
- derandomizing data read from the memory or randomizing data to be written to the memory using the initial RS data.
A memory device, comprising:
- a flash memory cell array;
- a random sequence (RS) data generator configured to generate at least one RS data string based on a first seed;
- a randomizing circuit configured to mix the RS data with data to be written to the flash memory cell array;
- a derandomizing circuit configured to derandomize data read from the flash memory cell array;
- and
- a control circuit configured to control access to the flash memory cell array and activate the RS data generator based on memory access mode, wherein the randomizing circuit and the derandomizing circuit are disposed between a page buffer and an I/O pin;
- wherein a portion of memory address is used as the first seed in one mode and a second seed is generated by the RS data generator in a second mode.
A memory system comprising:
- a memory device comprising:
- a flash memory cell array;
- a random sequence (RS) circuit configured to generate RS data;
- and
- a mixer configured to mix random sequence (RS) data with data to be written to the flash memory cell array and to derandomize data read from the flash memory cell array;
- a memory controller comprising a control circuit configured to control writing to and reading from the flash memory cell array through the mixer;
- and
- at least another memory device comprising a flash memory cell array and a random sequence circuit configured to mix random sequence RS data with data to be written to the flash memory cell array and to derandomize data read from the flash memory cell array.
A memory device, comprising:
- a flash memory cell array;
- a random sequence (RS) data generator configured to generate at least one RS data string based on a first seed;
- a mixer configured to derandomize data read from the flash memory cell array;
- and
- a control circuit configured to control access to the flash memory cell array and activate the RS data generator based on memory access mode, wherein a portion of memory address is used as the first seed in one mode and a second seed is generated by the RS data generator in a second mode.
Dependencies are inferred from the claim text.