US 8,751,714 B2Granted

Implementing quickpath interconnect protocol over a PCIe interface

AssigneeIntel Corporation

InventorsRobert J. Safranek, Debendra Das Sharma, Ganapati N. Srinivasa

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Abstract

Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry.

Claims22

Dependent claims

A system, comprising:

a plurality of processors, each having a local cache and operatively coupled to a respective memory store having a portion of shared memory for the system;
and
Peripheral Component Interconnect Express (PCIe) interconnect and interface circuitry, operatively coupling at least two of the processors, the PCIe interface circuitry including,
circuitry and logic to implement a PCIe Physical Layer (PHY) including a PCIe PHY logical sub-layer and a PCIe PHY electrical sublayer;
logic to implement a protocol layer, routing layer and link layer for a QuickPath Interconnect (QPI) protocol over the PCIe PHY;
logic to implement an interface between the QPI link layer and the PCIe PHY logical sub-layer under which the QPI link layer interface comprises a 160-bit (160b) interface and the PCIe PHY logical sub-layer interface comprises a 128-bit (128b) interface;
a transmit port including logic to implement a 160b to 128b conversion to interface data to be transmitted via the PCIe PHY from the QPI link layer interface to the PCIe PHY logical sub-layer interface;
and
a receive port including logic to implement a 128b to 160b conversion to interface data received at the receive port via the PCIe PHY from the PCIe PHY logical sub-layer interface to the QPI link layer interface,
wherein the at least two processors are configured to implement the QPI protocol using corresponding QPI messaging sent over PCIe interconnect and interface circuitry to support coherent memory transactions in the system.

7 more elements

A method, comprising:

implementing an link between a transmit port and a receive port employing a protocol layer, routing layer and link layer for a QuickPath Interconnect (QPI) protocol over a Peripheral Component Interconnect Express (PCIe) physical layer (PHY) comprising PCIe interconnect and interface circuitry, wherein the PCIe PHY includes a PCIe PHY logical sub-layer and a PCIe PHY electrical sub-layer;
implementing an interface between the QPI link layer and the PCIe PHY logical sub-layer under which the QPI link layer interface comprises an 160-bit (160b) interface and the PCIe PHY logical sub-layer interface comprises a 128-bit (128b) interface;
performing a 128b to 160b conversion when interfacing data from the PCIe PHY logical sub-layer interface to the QPI link layer interface;
performing a 160b to 128b conversion when interfacing data from the QPI link layer interface to the PCIe PHY logical sub-layer interface;
and
transmitting QPI data blocks over the interconnect link from the transmit port to the receive port using the 160b to 128b conversion at the transmit port and the 128b to 160b conversion at the receive port.

3 more elements

An apparatus comprising:

a PCIe Physical Layer (PHY) interface including circuitry and logic to implement a PCIe PHY including a PCIe PHY logical sub-layer and a PCIe PHY electrical sublayer;
logic to implement a protocol layer, routing layer and link layer for a QuickPath Interconnect (QPI) protocol over the PCIe PHY;
logic to implement an interface between the QPI link layer and the PCIe PHY logical sub-layer under which the QPI link layer interface comprises a 160-bit (160b) interface and the PCIe PHY logical sub-layer interface comprises a 128-bit (128b) interface;
a transmit port including logic to implement a 160b to 128b conversion to interface data to be transmitted via the PCIe PHY from the QPI link layer interface to the PCIe PHY logical sub-layer interface;
and
a receive port including logic to implement a 128b to 160b conversion to interface data received at the receive port via the PCIe PHY from the PCIe PHY logical sub-layer interface to the QPI link layer interface.

3 more elements

Dependencies are inferred from the claim text.