Memory controllers, memory systems, solid state drives and methods for processing a number of commands

A memory system, comprising:

• a number of memory devices;
• and
• a controller having:
• a front end direct memory access module (DMA);
• and
• a plurality of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA, each back end channel corresponding to a different memory device, the front end DMA being configured to:
• generate a number of back end commands at least in response to a number of the host commands in a command queue, wherein the number of back end commands is different than the number of the host commands, and
• distribute the number of back end commands to the plurality of back end channels, wherein the number of back end commands is at least equal to a quantity of the plurality of back end channels.

A memory system, comprising:

• a number of memory devices;
• and
• a controller having:
• a front end direct memory access module (DMA);
• and
• a number of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA, the front end DMA being configured to:
• determine a net read from the number of memory devices to be accomplished a number of read commands;
• and
• modify one or more of the number of read commands such that fewer commands are sent to accomplish the same net read from the number of memory devices in order to economize distribution of the number of read commands among the plurality of back end channels,
• wherein each of the number of back end channels corresponds to a different one of the number of memory devices.