Data transfer operation completion detection circuit and semiconductor memory device provided therewith

A device that can perform a data transfer operation in response to each of data transfer commands and can accept a new data transfer command while a data transfer operation responsive to a current data transfer command is in progress, comprising:

• a plurality of latch circuits each including a clock terminal, an input terminal and an output terminal, the latch circuits being connected in cascade such that the output terminal of a preceding one of the latch circuits is connected to the input terminal of a succeeding one of the latch circuits;
• a clock node supplied with a clock signal controlling the data transfer operation, the clock node being connected in common to the clock terminals of the latch circuits;
• an input node supplied with a transfer initiation signal that takes an active level each time the data transfer operation responsive to each data transfer command is initiated, the input node being connected to the input terminal of a leading one of the latch circuits;
• and
• a logic circuit coupled to the output terminals of the latch circuits, the logic circuit producing a first output signal when at least one of the latch circuits produces at the output terminal thereof a first logic level responsive to the active level of the transfer initiation signal and a second output signal when none of the latch circuits produces at the output terminal thereof the first logic level,
• wherein the data transfer operation is completed in a plurality of cycles of the clock signal that is responsive to an addition latency (AL), a CAS latency (CL) and a burst length (BL).

A device that can perform a data transfer operation in response to each of data transfer commands and can accept a new data transfer command while a data transfer operation responsive to a current data transfer command is in progress, comprising;

• a plurality of latch circuits each including a clock terminal, an input terminal and an output terminal, the latch circuits being connected in cascade such that the output terminal of a preceding one of the latch circuits is connected to the input terminal of a succeeding one of the latch circuits;
• a clock node supplied with a clock signal controlling the data transfer operation, the clock node being connected in common to the clock terminals of the latch circuits;
• an input node supplied with a transfer initiation signal that takes an active level each time the data transfer operation responsive to each data transfer command is initiated, the input node being connected to the input terminal of a leading one of the latch circuits;
• and
• a logic circuit coupled to the output terminals of the latch circuits, the logic circuit producing a first output signal when at least one of the latch circuits produces at the output terminal thereof a first logic level responsive to the active level of the transfer initiation signal and a second output signal when none of the latch circuits produces at the output terminal thereof the first logic level;
• wherein the device accepts a power-down command and further comprises a power-down control circuit that responds to the power-down command and the second output signal of the logic circuit to cause the device to enter into a power-down mode.