Simulation using parallel processors

A method for design simulation, comprising:

• partitioning a logical verification task of a design into a first plurality of atomic Processing Elements (PEs);
• determining execution dependencies between the PEs, each execution dependency specifying that a respective first PE is to be executed before a respective second PE;
• providing a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device;
• computing an order for executing the PEs on the multiprocessor device, the order formed of a sequence of slots to which the PEs are assigned, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE such that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device;
• providing the PEs and the computed order to the multiprocessor device for execution according to the scheduling policy, so as to produce a simulation result;
• and
• verifying a performance of the design responsively to the simulation result,
• wherein partitioning the verification task comprises identifying multiple subsets of the PEs, such that each subset comprises the PEs that are affected by a respective external event applied to the design, and wherein computing the order comprises determining respective orders within each of the subsets.

A method for design simulation, comprising:

• partitioning a logical verification task of a design into a first plurality of atomic Processing Elements (PEs);
• determining execution dependencies between the PEs, each execution dependency specifying that a respective first PE is to be executed before a respective second PE;
• providing a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device;
• computing an order for executing the PEs on the multiprocessor device, the order formed of a sequence of slots to which the PEs are assigned, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE such that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device;
• providing the PEs and the computed order to the multiprocessor device for execution according to the scheduling policy, so as to produce a simulation result;
• and
• verifying a performance of the design responsively to the simulation result,
• wherein the processors in the multiprocessor device are arranged in modules, such that the processors in each module access a device memory of the multiprocessor device jointly, wherein computing the order comprises grouping the PEs in PE Groups (PEGs),
• wherein grouping the PEs comprises maximizing respective sizes of the PEGs while minimizing respective numbers of outputs provided to the PEGs, and
• wherein executing the PEs comprises executing each PEG by a respective module.

A method for design simulation, comprising:

• partitioning a logical verification task of a design into a first plurality of atomic Processing Elements (PEs);
• determining execution dependencies between the PEs, each execution dependency specifying that a respective first PE is to be executed before a respective second PE;
• providing a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device;
• computing an order for executing the PEs on the multiprocessor device, the order formed of a sequence of slots to which the PEs are assigned, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE such that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device;
• providing the PEs and the computed order to the multiprocessor device for execution according to the scheduling policy, so as to produce a simulation result;
• and
• verifying a performance of the design responsively to the simulation result,
• wherein the processors in the multiprocessor device are arranged in modules, such that the processors in each module access a device memory of the multiprocessor device jointly, wherein computing the order comprises grouping the PEs in PE Groups (PEGs), and
• wherein grouping the PEs comprises maximizing respective sizes of the PEGs while minimizing respective numbers of inputs provided to the PEGs.

A method for design simulation, comprising:

• partitioning a logical verification task of a design into a first plurality of atomic Processing Elements (PEs);
• determining execution dependencies between the PEs, each execution dependency specifying that a respective first PE is to be executed before a respective second PE;
• providing a multiprocessor device which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device;
• computing an order for executing the PEs on the multiprocessor device, the order formed of a sequence of slots to which the PEs are assigned, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE such that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device;
• providing the PEs and the computed order to the multiprocessor device for execution according to the scheduling policy, so as to produce a simulation result;
• and
• verifying a performance of the design responsively to the simulation result,
• wherein executing the PEs comprises evaluating simulation state values at respective time intervals, and storing the simulation state values in at least one operational mode selected from a group of modes consisting of a continuous mode in which the simulation state values are stored continuously, and a snapshot mode in which only selected snapshots of the simulation state values are stored.

A computing method, comprising:

• representing a computing task by a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE;
• computing an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the multiprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device;
• and
• executing the PEs on the processors in accordance with the computed order and the scheduling policy, to produce a result of the computing task,
• wherein computing the order comprises preserving the execution dependencies by inserting dummy PEs into the order.

Apparatus for design simulation, comprising:

• an interface, which is coupled to accept a definition of a verification task of a design to be simulated;
• and
• a Central Processing Unit (CPU), which is arranged to partition the definition into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE, to compute an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device, and to cause the processors to execute the PEs in accordance with the computed order and the scheduling policy so as to simulate the design,
• wherein the CPU is arranged to identify multiple subsets of the PEs, such that each subset comprises the PEs that are affected by a respective external event applied to the design, and to compute respective orders for executing the PEs within each of the subsets.

Apparatus for design simulation, comprising:

• an interface, which is coupled to accept a definition of a verification task of a design to be simulated;
• and
• a Central Processing Unit (CPU), which is arranged to partition the definition into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE, to compute an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device, and to cause the processors to execute the PEs in accordance with the computed order and the scheduling policy so as to simulate the design,
• wherein the CPU is arranged to preserve the execution dependencies by inserting dummy PEs into the order.

Apparatus for design simulation, comprising:

• an interface, which is coupled to accept a definition of a verification task of a design to be simulated;
• and
• a Central Processing Unit (CPU), which is arranged to partition the definition into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE, to compute an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device, and to cause the processors to execute the PEs in accordance with the computed order and the scheduling policy so as to simulate the design,
• wherein the processors in the multiprocessor device are arranged in modules, such that the processors in each module access a device memory of the multiprocessor device jointly, and wherein the CPU is arranged to group the PEs in PE Groups (PEGs) and to cause the multiprocessor device to execute each PEG by a respective module,
• wherein the CPU is arranged to group the PEs by maximizing respective sizes of the PEGs while minimizing respective numbers of inputs provided to the PEGs.

Apparatus for design simulation, comprising:

• an interface, which is coupled to accept a definition of a verification task of a design to be simulated;
• and
• a Central Processing Unit (CPU), which is arranged to partition the definition into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE, to compute an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device, and to cause the processors to execute the PEs in accordance with the computed order and the scheduling policy so as to simulate the design,
• wherein the CPU is arranged to evaluate simulation state values at respective time intervals, and to store the simulation state values in at least one operational mode selected from a group of modes consisting of a continuous mode in which the simulation state values are stored continuously, and a snapshot mode in which only selected snapshots of the simulation state values are stored.

Apparatus for design simulation, comprising:

• a multiprocessor device, which comprises multiple processors configured to operate in parallel and schedules execution by the processors according to a built-in scheduling policy;
• and
• a Central Processing Unit (CPU), which is arranged to partition the definition of a verification task of a design into a plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a first respective PE is to be executed before a second respective PE, to compute an order for executing the PEs on the multiple processors of the multiprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device, and to cause the processors to execute the PEs in accordance with the computed order and the scheduling policy so as to simulate the design,
• wherein the CPU is arranged to preserve the execution dependencies by inserting dummy PEs into the order.

A computing apparatus, comprising:

• an interface, which is coupled to accept a definition of computing task;
• and
• a Central Processing Unit (CPU), which is arranged to partition the definition into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE, to compute an order for executing the PEs on a multiprocessor device, which comprises a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy of the microprocessor device, such that each second PE depending on a first PE is located in the order at least a predetermined number of slots after the respective first PE so that the order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy of the multiprocessor device, and to cause the processors to execute the PEs in accordance with the computed order and the scheduling policy so as to produce a result of the computing task,
• wherein the CPU is arranged to preserve the execution dependencies by inserting dummy PEs into the order.