US 8,751,210 B1Granted

Suspending procedures in simulation of a circuit design

AssigneeXilinx, Inc.

InventorSonal Santan

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Abstract

When a wait statement is encountered in an HDL simulation, the simulation kernel executes functions corresponding to other processes while waiting for the wait to mature. However, the preservation of variables and states of each process and procedure in the call chain can be complex and inefficient. An embodiment of the present invention provides a method to suspend procedures in simulation of an HDL circuit design such that processes that call procedures containing wait statements are executed on a secondary runtime stack and can be suspended by saving the state of simulation and switching simulation execution to the primary runtime stack.

Claims20

Dependent claims

A method of simulating a circuit design comprising:

loading a specification of the circuit design into a first runtime stack;
simulating the circuit design specification on a simulator in the first runtime stack;
in response to each call during simulation to each first process contained in the specification and having no call to a procedure that contains a wait statement:
loading the first process into the first runtime stack;
and
executing statements of the first process;
in response to a call during simulation to a second process contained in the specification and having a call to a procedure containing a wait statement:
saving a first state corresponding to the current state of simulation;
loading the second process into a second runtime stack;
and
setting the current state of simulation to a state for continuing simulating with the second process in the second runtime stack;
and
in response to a wait statement encountered in the procedure called by the second process during simulation of the second process in the second runtime stack:
saving a second state corresponding to the current state of simulation;
and
setting the current state of simulation to the first state for continuing simulating of the specification in the first runtime stack;
in response to the simulator determining the wait statement has expired, performing the steps of:
saving a third state corresponding to the current state of the simulation;
and
setting the current state of the simulation to the second state for continuing simulating of the second process in the second runtime stack;
in response to completing the simulation of the second process in the second runtime stack, setting the current state of the simulation to the third state for continuing simulating of the specification in the first runtime stack.

18 more elements

A method to compile an HDL specification for simulation comprising:

creating a second intermediate process corresponding to a first process of the specification that contains a call to a procedure containing a wait statement;
replacing calls to the first process in the HDL specification with calls to the second intermediate process;
appending the second intermediate process to the modified HDL specification;
compiling the appended HDL specification into a form executable on a simulator;
storing the compiled executable form;
wherein the executable specification loads a first runtime stack when executed;
and
wherein the second intermediate process comprises:
loading the first process and the procedure into a second runtime stack;
saving a first state corresponding to the current CPU state;
setting the current CPU state to a state to execute the first process and procedure in the second runtime stack;
and
in response to a wait statement encountered during execution of the first process and procedure loaded in the second runtime stack, performing the steps of:
saving a second state corresponding to the current CPU state;
and
setting the current CPU state to that of the first state to continue
execution of the executable specification in the first runtime stack.

14 more elements

A system for simulating a circuit design specification comprising:

a processor;
a common bus coupled to the processor;
a memory unit coupled to the common bus;
and
an input/output unit coupled to a common bus;
wherein, the processor and memory are configured to:
implement a first and second memory stack in the memory unit;
load a specification of the circuit design into the first memory stack;
in response to each call during simulation of the specification to each first process contained in the specification and having no call to a procedure that contains a wait statement, simulate the first process on the first memory stack;
wherein, in response to a call during simulation to a second process contained in the specification and calls a procedure containing a wait statement, the processor and memory are further configured to:
load the second process into the second memory stack;
determine and store a first state corresponding to the current state of the system;
and
set the current state of the system to a state for simulation of the second process on the second memory stack;
and
wherein, in response to a wait statement encountered in the procedure called by the second process during simulation of the second process, the processor and memory are further configured to:
save a second state corresponding to the current state of the system;
and
set the context state of the system to that of the first context state to continue simulation of the specification on the first memory stack;
in response to an expiration of the wait statement;
save a third state corresponding to the current state of the system;
and
set the current state of the system to that of the second state to continue simulation of the second process and the procedure called by the second process on the second memory stack;
in response to completing the simulation of the second process, set the current state of the simulation to that of the third state to continue simulation of the specification on the first memory stack.

21 more elements

Dependencies are inferred from the claim text.

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Abstract