US 8,751,182 B2Granted

System and method for testing serial ports

AssigneesHONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., Hon Hai Precision Industry Co., Ltd.

InventorsZhi-Jian Long, Ming-Xiang Hu, Jun-Min Chen, Le Lin, Xiao-Fei Chen

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Abstract

In a system and method for testing a serial port of a computing device, the serial port electronically connects to a test fixture. Test data is sent to a receive data (RXD) pin by a transmit data (TXD) pin. A test result is received from the serial port by the RXD pin. The TXD pin and the RXD pin work normally if the test data is identical to the test result. When voltages of a request to send (RTS) pin and a data terminal ready (DTR) pin are set at high level, the RTS pin, a data carrier detect (DCD) pin, the DTR pin, a ring indicator (RI) pin, a data send ready (DSR) pin and a clear to send (CTS) pin work normally, upon the condition that status values of the serial port indicate the voltages of the above six pins are at high level.

Claims19

Dependent claims

A computing device, comprising:

a storage system;
at least one processor;
a motherboard comprising a serial port;
and
one or more programs stored in the storage system and executed by the at least one processor, the one or more programs comprising:
a sending module operable to enable a transmit data (TXD) pin of the serial port to send test data to a receive data (RXD) pin of the serial port;
an acquisition module operable to enable the RXD pin to receive a test result from the serial port, and acquire status values of the serial port;
a determination module operable to compare the test data with the test result, and determine that the TXD pin and the RXD pin work normally upon the condition that the test data is identical to the test result;
a setting module operable to set voltages of a data terminal ready (DTR) pin and a request to send (RTS) pin of the serial port at high level;
the determination module further operable to determine that the RTS pin and a data carrier detect (DCD) pin of the serial port work normally, upon the condition that the status values indicate the voltages of the RTS pin and the DCD pin are at high level;
the determination module further operable to determine that the DTR pin and a ring indicator (RI) pin of the serial port work normally, upon the condition that the status values indicate the voltages of the DTR pin and the RI pin are at high level;
and
the determination module further operable to determine that a data send ready (DSR) pin and a clear to send (CTS) pin of the serial port work normally, upon the condition that the status values indicate the voltages of the DSR pin and the CTS pin are at high level.

10 more elements

A method for testing a serial port of a computing device, the method comprising:

(a) enabling a transmit data (TXD) pin of the serial port to send test data to a receive data (RXD) pin of the serial port, and enabling the RXD pin to receive a test result from the serial port;
(b) comparing the test data with the test result, and determining that the TXD pin and the RXD pin work normally upon the condition that the test data is identical to the test result;
(c) acquiring a first status values of the serial port when a voltage of a request to send (RTS) pin of the serial port is set at high level;
(d) determining that the RTS pin and a data carrier detect (DCD) pin of the serial port work normally, upon the condition that the first status values indicate the voltages of the RTS pin and the DCD pin are at high level;
(e) acquiring a second status values of the serial port when a voltage of a data terminal ready (DTR) pin of the serial port is set at high level;
(f) determining that the DTR pin and a ring indicator (RI) pin of the serial port work normally, upon the condition that the second status values indicate the voltages of the DTR pin and the RI pin are at high level;
(g) acquiring a third status values of the serial port when the voltages of the RTS pin and DTR pin are set at high level;
and
(h) determining that a data send ready (DSR) pin and a clear to send (CTS) pin of the serial port work normally, upon the condition that the third status values indicate the voltages of the DSR pin and the CTS pin are at high level.

6 more elements

A non-transitory storage medium storing a set of instructions, the set of instructions capable of being executed by a processor of a computing device, causes the computing device to execute a method for testing a serial port of the computing device, the method comprising:

(a) enabling a transmit data (TXD) pin of the serial port to send test data to a receive data (RXD) pin of the serial port, and enabling the RXD pin to receive a test result from the serial port;
(b) comparing the test data with the test result, and determining that the TXD pin and the RXD pin work normally upon the condition that the test data is identical to the test result;
(c) acquiring a first status values of the serial port when a voltage of a request to send (RTS) pin of the serial port is set at high level;
(d) determining that the RTS pin and a data carrier detect (DCD) pin of the serial port work normally, upon the condition that the first status values indicate the voltages of the RTS pin and the DCD pin are at high level;
(e) acquiring a second status values of the serial port when a voltage of a data terminal ready (DTR) pin of the serial port is set at high level;
(f) determining that the DTR pin and a ring indicator (RI) pin of the serial port work normally, upon the condition that the second status values indicate the voltages of the DTR pin and the RI pin are at high level;
(g) acquiring a third status values of the serial port when the voltages of the RTS pin and DTR pin are set at high level;
and
(h) determining that a data send ready (DSR) pin and a clear to send (CTS) pin of the serial port work normally, upon the condition that the third status values indicate the voltages of the DSR pin and the CTS pin are at high level.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/209,449Filed 15 Aug 2011
Priority: CN 2010 1 050830814 Oct 2010
Published: US 2012/0095717 A119 Apr 2012
Granted: 10 Jun 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 11/221
Using arrangements specific to the hardware being tested: to test buses, lines or interfaces, e.g. stuck-at or open line faults
G06F 11/2221
Using arrangements specific to the hardware being tested: to test input/output devices or peripheral units
G06F 11/2284
Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing: by power-on…
G06F 11/25
Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing: testing of…

Family

US 2012/0095717 A1Pre-grant publication · published 19 Apr 2012
US 8,751,182 B2This patent

From the US filing history. Foreign family members aren’t listed.

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