Sub-resolution assist feature repair
AssigneeMentor Graphics Corporation
InventorsJames Word, Kyohei Sakajiri
Life of this patent
Estimating the term…
Abstract
After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof.
Claims10
One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
- receiving information of a layout design, the layout design representing at least a portion of an integrated circuit design;
- performing a resolution enhancement process on the layout design to generate an altered layout design;
- checking the altered layout design for errors, wherein one or more errors are detected and comprise one or more sub-resolution assist feature errors and one or more main feature errors;
- performing a repair process to correct the one or more detected sub-resolution assist feature errors;
- saving the corrected layout design to a memory storage location;
- A. forming a re-correction region around at least one of the one or more main feature errors, wherein the re-correction region designates a sub-portion of the altered layout design;
- B. identifying a second set of parameter values different than the first set of parameter values employed by the resolution enhancement process;
- C. performing an optical proximity correction process that employs the second set of parameter values on the re-correction region to generate an altered re-correction region;
- and
- D. stitching the altered re-correction region into the altered layout design to generate a modified layout design.
A method, comprising:
- with a computer,
- receiving information of a layout design, the layout design representing at least a portion of an integrated circuit design;
- performing a resolution enhancement process on the layout design to generate an altered layout design;
- checking the altered layout design for errors, wherein one or more errors are detected and comprise one or more sub-resolution assist feature errors and one or more main feature errors;
- performing a repair process to correct the one or more detected sub-resolution assist feature errors;
- saving the corrected layout design to a memory storage location;
- and
- A. forming a re-correction region around at least one of the one or more main feature errors, wherein the re-correction region designates a sub-portion of the altered layout design;
- B. identifying a second set of parameter values different than the first set of parameter values employed by the resolution enhancement process;
- C. performing an optical proximity correction process that employs the second set of parameter values on the re-correction region to generate an altered re-correction region;
- and
- D. stitching the altered re-correction region into the altered layout design to generate a modified layout design.
Dependencies are inferred from the claim text.