US 8,710,592 B2 · SRAM cells using shared gate electrode configuration

Abstract

An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.

Claims20

Dependent claims

An SRAM cell comprising:

a first PMOS active region and a second PMOS active region defined in a semiconductor substrate;
a first NMOS active region and a second NMOS active region defined in the semiconductor substrate, the first and second NMOS active regions being disposed between the first PMOS active region and the second PMOS active region;
a first PMOS pass gate crossing Over the first PMOS active region;
a first NMOS pass gate crossing over the first NMOS active region;
a first shared gate crossing over the first PMOS active region and the first NMOS active region;
a second PMOS pass gate crossing over the second PMOS active region;
a second NMOS pass gate crossing over the second NMOS active region;
and
a second shared gate crossing over the second PMOS active region and the second NMOS active region.

6 more elements

An SRAM cell comprising:

elongate first and second PMOS active regions and elongate first and second NMOS active regions arranged in a row in a semiconductor substrate, the first and second NMOS active regions disposed between the first and second PMOS active regions;
a first PMOS pass transistor comprising a first gate electrode disposed on the first PMOS active region;
a first NMOS pass transistor comprising a second gate electrode disposed on the first NMOS active region;
a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween;
a second PMOS pass transistor comprising a fourth gate electrode disposed on the second PMOS active region;
a second NMOS pass transistor comprising a fifth gate electrode disposed on the second NMOS active region;
and
a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.

5 more elements

Dependencies are inferred from the claim text.

SRAM cells using shared gate electrode configuration

Life of this patent

SRAM cells using shared gate electrode configuration

Life of this patent

Abstract

Claims20