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US 8,710,569 B2Granted
Semiconductor device and manufacturing method thereof
AssigneeRenesas Electronics Corporation
InventorsKen Inoue, Masayuki Hamada
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.
Claims17
A semiconductor device comprising:
- a semiconductor substrate comprising a dynamic random access memory (DRAM) portion and a logic portion thereon;
- a first transistor formed in said DRAM portion and comprising source and drain regions and a metal silicide layer comprising one of cobalt silicide and nickel silicide formed on said source and drain regions;
- a second transistor having a conductivity type which is the same as a conductivity type of the first transistor, and formed in said logic portion and comprising source and drain regions, said metal silicide layer being formed on said source and drain regions of said second transistor;
- a third transistor formed in said logic portion and having a conductivity type which is different than the conductivity type of the first and second transistors, and comprising source and drain regions, said metal silicide layer being formed on said source and drain regions of said third transistor;
- an interlayer film covering said DRAM portion and logic portion of said semiconductor substrate;
- a capacitor formed on said interlayer film in said DRAM portion and comprising a lower electrode;
- and
- plural contact plugs, said plural contact plugs being formed in said interlayer film in said DRAM portion and said logic portion,
- wherein said source and drain regions of said first, second and third transistors comprise respective first and second diffusion regions, said second diffusion region comprising a lightly-doped region and said first diffusion region comprising a highly-doped region having
- an impurity density which is greater than an impurity density of said second diffusion region,
- wherein said metal silicide layer is formed on a substantially entire surface of said highly-doped region of said source and drain regions of said first, second and third transistors in the DRAM and logic portions, an interface between said metal silicide layer and said substantially entire surface of said highly-doped region of said source and drain regions of the first, second and third transistors in said DRAM portion and said logic portion being located under a main surface of said substrate,
- wherein said plural contact plugs are in contact with said metal silicide layer on said highly-doped region of said source and drain regions of said first, second and third transistors in said DRAM portion and said logic portion, and comprise a capacitor contact which is in contact with said lower electrode of said capacitor, an interface between said plural contact plugs and said metal silicide layer being formed at said main surface in said DRAM portion and said logic portion,
- wherein said metal silicide layer comprises a silicided surface of said semiconductor substrate,
- wherein said plural contact plugs comprise a bit line contact formed on said metal silicide layer on said source and drain regions of said first, second and third transistors,
- wherein each of said first, second and third transistors further comprises a gate electrode, said metal silicide layer being formed on said gate electrode, and
- wherein the semiconductor device further comprises:
- another interlayer film formed on said interlayer film and said capacitor, said bit line contact being formed in said interlayer film and said another interlayer film;
- and
- an interconnection which serves as a bit line and is formed on said another interlayer film and connected to said bit line contact.
16 more elements
A semiconductor device comprising:
- a semiconductor substrate comprising a dynamic random access memory (DRAM) portion and a logic portion thereon;
- a first transistor formed in said DRAM portion and comprising source and drain regions;
- a second transistor having a conductivity type which is the same as a conductivity type of the first transistor, and formed in said logic portion and comprising source and drain regions;
- a third transistor formed in said logic portion and having a conductivity type which is different than the conductivity type of the first and second transistors, and comprising source and drain regions, the source and drain regions of the first, second and third transistors including respective first and second diffusion regions, said second diffusion region comprising a lightly-doped region and said first diffusion region comprising a highly-doped region having an impurity density which is greater than an impurity density of said second diffusion region;
- a metal silicide layer comprising one of cobalt silicide and nickel silicide formed on a substantially entire surface of said highly-doped region of said source and drain regions of said first, second and third transistors, an interface between said metal silicide layer and said substantially entire surface of said highly-doped region of said source and drain regions in said first, second and third transistors being located under a main surface of said substrate;
- an interlayer film covering said DRAM portion and logic portion of said semiconductor substrate;
- and
- plural contact plugs, said plural contact plugs being formed in said interlayer film in said DRAM portion and said logic portion, said plural contact plugs being in contact with said metal silicide layer on said highly-doped region of said source and drain regions of said first, second and third transistors in said DRAM portion and said logic portion, an interface between said plural contact plugs and said metal silicide layer being formed at said main surface in said DRAM portion and said logic portion,
- wherein said metal silicide layer comprises a silicided surface of said semiconductor substrate,
- wherein said plural contact plugs comprise a bit line contact formed on said metal silicide layer on said source and drain regions of said first, second and third transistors,
- wherein each of said first, second and third transistors further comprises a gate electrode, said metal silicide layer being formed on said gate electrode, and
- wherein the semiconductor device further comprises:
- another interlayer film formed on said interlayer film and said upper electrode of said capacitor, said bit line contact being formed in said interlayer film and said another interlayer film;
- and
- an interconnection which serves as a bit line and is formed on said another interlayer film and connected to said bit line contact.
12 more elements
Dependencies are inferred from the claim text.