Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structure
AssigneeGlobalfoundries Inc.
InventorsThilo Scheiper, Kerstin Ruttloff, Maciej Wiatr, Stefan Flachowsky
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Abstract
In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.
Claims24
A method, comprising:
- forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, said first and second gate electrode structures comprising a dielectric cap layer;
- forming a sacrificial spacer adjacent to sidewalls of said first and second gate electrode structures;
- removing said dielectric cap layer from each of said first and second gate electrode structures in the presence of said sacrificial spacer;
- after removing said dielectric cap layers, forming deep drain and source regions selectively in said first active region by using said sacrificial spacer as an implantation mask;
- removing said sacrificial spacer from said first and second gate electrode structures;
- and
- forming deep drain and source regions selectively in said second active region after removal of said sacrificial spacer.
A method of forming transistors of a semiconductor device, the method comprising:
- forming a first gate electrode structure on a first active region and forming a second gate electrode structure on a second active region, at least one of said first and second gate electrode structures comprising a gate dielectric layer including a high-k dielectric material;
- forming a sacrificial spacer adjacent to sidewalls of said first and second gate electrode structures;
- removing a dielectric cap layer from said first and second gate electrode structures by using said sacrificial spacer as an etch mask;
- after removing said dielectric cap layer, forming first deep drain and source regions selectively in said first active region by using said sacrificial spacer as an implantation mask;
- removing said sacrificial spacer from said first and second gate electrode structures;
- and
- forming second deep drain and source regions selectively in said second active region by using a spacer element formed adjacent to sidewalls of said first and second gate electrode structures after removal of said sacrificial spacer.
A method of forming a semiconductor device, the method comprising:
- forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, said first and second gate electrode structures comprising a high-k gate dielectric material and a dielectric cap layer;
- forming a first spacer structure adjacent to sidewalls of said first and second gate electrode structures;
- removing said dielectric cap layer from said first and second gate electrode structures by using said first spacer structure as an etch mask;
- forming first deep drain and source regions in said first active region in the presence of said first spacer structure, wherein an outer sidewall surface of said first spacer structure formed adjacent to said first gate electrode structure is directly exposed to an implantation process that is used to form said first deep drain and source regions;
- and
- forming second deep drain and source regions in said second active region by using a second spacer structure.
A method of forming a semiconductor device, the method comprising:
- forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, said first and second gate electrode structures comprising a high-k gate dielectric material and a dielectric cap layer;
- forming a first spacer structure on sidewalls of said first and second gate electrode structures;
- removing said dielectric cap layer from said first and second gate electrode structures by using said first spacer structure as an etch mask;
- forming first deep drain and source regions in said first active region in the presence of said first spacer structure;
- and
- forming second deep drain and source regions in said second active region by using a second spacer structure, wherein forming said second deep drain and source regions comprises removing said first spacer structure and forming said second spacer structure after removal of said first spacer structure.
Dependencies are inferred from the claim text.