Method to dynamically tune precision resistance
AssigneeGlobalfoundries Inc.
InventorsSteven R. Soss, Andreas Knorr
Life of this patent
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Abstract
A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
Claims8
A method of fabricating a resistor, the method comprising:
- forming a resistive semiconductive element in a polycrystalline gate line, by patterning a portion of the polycrystalline gate line, the resistive semiconductive element having a width and a length, wherein the length and/or width of the resistive semiconductive element is less than a length and/or width, respectively, of the polycrystalline gate line;
- patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom;
- and
- forming a depletion channel in the resistive semiconductive element under the electrically conductive line to form a resistance in series with the resistive semiconductive element.
A method of fabricating a semiconductor device comprising:
- patterning a polycrystalline gate line on a substrate;
- forming a resistive semiconductive element, having a width and a length, in the polycrystalline gate line, by patterning a portion of the polycrystalline gate line, wherein the width and/or length of the resistive semiconductor element is less than a width and/or length, respectively, of the polycrystalline gate line;
- forming a dielectric layer to a thickness of about 10 nm to about 20 nm over the resistive semiconductive element;
- self aligning a contact layer to the gate line, over the dielectric layer, to a width of about 20 nm to about 40 nm along the length of the resistive semiconductive element, thereby forming an electrically conductive line across the width of the resistive semiconductive element;
- and
- dynamically applying a bias voltage of about 0.8 V to about 5 V to the electrically conductive line to form a depletion channel to a width of about 10 nm or less in the resistive semiconductive element under the electrically conductive line, to dynamically control the resistance value of the resistive semiconductive element.
Dependencies are inferred from the claim text.