Power management in semiconductor memory system
AssigneeInphi Corporation
InventorDavid T. Wang
Life of this patent
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Abstract
A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.
Claims15
A method for operating a memory module device, the method comprising:
- transferring a chip select, command, and address information from a host memory controller, the host memory controller being coupled to a memory interface device, the memory interface device being coupled to a memory module, the memory module comprising a plurality of memory devices;
- receiving the chip select, command, and address information at the memory interface device using a command-and-address-latency (CAL) mode;
- using a control logic to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.
A method for operating a memory module device, the method comprising:
- receiving a chip select signal at a memory interface device;
- receiving an address signal at the memory interface device;
- receiving a command signal at the memory interface device;
- receiving a parity signal at the memory interface device;
- transferring the chip select signal having a first latency from the memory interface device to a rank of DRAM devices;
- transferring the address signal and the command signal having a second latency from the memory interface device to the rank of DRAM devices;
- transferring the parity signal having a third latency from the memory interface device to the rank of DRAM devices;
- and
- causing each of the DRAM devices to initiate a power state transition from a first power state to a second power state.
A memory module device comprising:
- an interface device configured for receiving a chip select, command, and address information from a host memory controller, the host memory controller being coupled to the memory interface device, the memory interface device being coupled to a memory module, the memory module comprising a plurality of memory devices, and configured for receiving the chip select, command, and address information at the memory interface device using a command-and-address-latency (CAL) mode;
- and a control logic to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.
Dependencies are inferred from the claim text.