Methods for optimizing conductor patterns for ECP and CMP in semiconductor processing

A method, comprising:

• using a computing device having a non-transitory computer memory storing executable programs, performing:
• retrieving layout data from the non-transitory computer memory for a design to be manufactured using an electrochemical plating (ECP) process forming patterned conductors in at least one metal layer over a semiconductor wafer;
• determining from the layout data, for each one of a plurality of unit grid areas covering the semiconductor wafer, a layout effects factor corresponding to one selected from a line edge density and a conductor pattern density in the at least one metal layer in the unit grid area;
• determining from the layout data a global effects factor corresponding to a total area of the metal layer on the semiconductor wafer over a total area of the semiconductor wafer;
• determining from the layout data a local effects factor for each of the unit grid areas, the local effects factor corresponding to a local pattern density of the at least one metal layer over a surface area of a local area that is larger than and includes the corresponding unit grid area;
• using the computing device, executing an ECP simulation using at least one of the global effects factor and the local effects factor as inputs, and using the layout effects factor as an input, to determine a predicted post-ECP hump height of the at least one metal layer for each of the unit grid areas;
• storing in the non-transitory computer memory a predicted post-ECP hump data map;
• and
• determining from the predicted post-ECP hump data map whether the at least one metal layer will have a post-ECP hump height on the semiconductor wafer that exceeds a predetermined post-ECP hump height threshold.

A non-transitory computer readable medium containing executable instructions that, when executed by a computing device, cause the computing device to perform:

• retrieving layout data from the non-transitory computer readable medium for forming patterned conductors in at least one metal layer over a semiconductor wafer in an electrochemical plating (ECP) process;
• determining from the layout data a global effects factor corresponding to a total area in the at least one metal layer on the semiconductor wafer over a total area of the semiconductor wafer;
• determining from the layout data a layout effects factor for each of a plurality of unit grid areas covering the semiconductor wafer, the layout effects factor corresponding to a pattern density of the at least one metal layer;
• determining from the layout data a local effects factor for each unit grid area, each local effects factor corresponding to the total area of the at least one metal layer over the area of the semiconductor wafer in a local area that is larger than and includes the corresponding unit grid area;
• using the computing device, executing an ECP simulation using at least one of the global effects factor and the local effects factor, and using the layout effects factor for each unit grid area, to predict a post-ECP hump height of the at least one metal layer for each unit grid area;
• storing in the non-transitory computer readable medium a predicted post-ECP hump data map output from the ECP simulation;
• responsive to the post-ECP hump data map, modifying the layout for the at least one metal layer;
• and
• outputting a photomask generation file for the at least one metal layer.