Automatic layout conversion for FinFET device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
Estimating the term…
A method for generating a layout for a FinFET device is disclosed. The method includes receiving an initial layout containing an active region that has an edge extending in a first direction. The method includes designating a portion of the layout as a first region. The first region contains the active region. The method includes designating an elongate portion of the first region as a second region that extends in the first direction. The method includes designating a different elongate portion of the first region as a third region that extends in the first direction and that is adjacent to the second region in a second direction perpendicular to the first direction. The method includes enlarging the active region if the edge of the active region falls inside the third region, and shrinking the active region if the edge of the active region falls outside the third region.
A method of generating a layout for a semiconductor device, comprising:
A method, comprising:
An apparatus comprising a non-transitory, tangible computer readable storage medium storing a computer program for modifying a layout of a semiconductor device, wherein the computer program has instructions that when executed, carry out:
Dependencies are inferred from the claim text.