Complementary metal oxide semiconductor (CMOS) buffer
AssigneeAdvanced Micro Devices, Inc.
InventorsOleg Drapkin, Grigori Temkine
Life of this patent
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Abstract
The present invention provides embodiments of an apparatus that includes a pad configurable for connection to a voltage source that provides a first voltage and a buffer connected to the pad. The buffer includes a plurality of transistors that have nominal breakdown voltages that are less than the first voltage. The buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the break-down voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.
Claims18
An apparatus, comprising:
- a pad configurable for connection to a voltage source that provides a first voltage;
- and
- a buffer connected to the pad, wherein the buffer comprises a plurality of transistors that have nominal breakdown voltages that are less than the first voltage, the plurality of transistors comprising a PMOS transistor and an NMOS transistor connected in series between the pad and ground, and wherein the buffer is configured to maintain voltage differentials on the plurality of transistors that are less than a breakdown voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage, and wherein the first voltage is higher than the breakdown voltage.
An apparatus, comprising:
- a pad configurable for connection to a voltage source that provides a first voltage;
- a buffer connected to the pad, wherein the buffer comprises a plurality of transistors that have a breakdown voltage that is less than the first voltage, wherein the plurality of transistors comprises a PMOS transistor and an NMOS transistor connected in series between the pad and ground;
- and
- core logic communicatively coupled to the buffer, wherein the core logic is configurable to provide a data signal and input signals to the buffer to drive a pad voltage to a value indicated by the data signal, and wherein the buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the breakdown voltage during pull-down of the pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.
A non-transitory computer readable medium including instructions that when executed configure a manufacturing process used to manufacture a semiconductor device comprising:
- a pad configurable for connection to a voltage source that provides a first voltage;
- and
- a buffer connected to the pad, wherein the buffer comprises a plurality of transistors that have a breakdown voltage that is less than the first voltage, the plurality of transistors comprising a PMOS transistor and an NMOS transistor connected in series between the pad and ground, and wherein the buffer is configured to maintain voltage differentials on the plurality of transistors that are less than a breakdown voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage, and wherein the first voltage is higher than the breakdown voltage.
A non-transitory computer readable medium including instructions that when executed configure a manufacturing process used to manufacture a semiconductor device comprising:
- a pad configurable for connection to a voltage source that provides a first voltage;
- a buffer connected to the pad, wherein the buffer comprises a plurality of transistors that have a breakdown voltage that is less than the first voltage, and wherein the plurality of transistors comprises a PMOS transistor and an NMOS transistor connected in series between the pad and ground;
- and
- core logic communicatively coupled to the buffer, wherein the core logic is configurable to provide a data signal and input signals to the buffer to drive a pad voltage to a value indicated by the data signal, and wherein the buffer is configured to maintain voltage differentials on the plurality of transistors that are less than a break down voltage of the plurality of transistors during pull-down of the pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage, and wherein the first voltage is higher than the breakdown voltage.
Dependencies are inferred from the claim text.