Dummy pattern design for thermal annealing

A semiconductor structure, comprising:

• a semiconductor substrate having a device region and a dummy region adjacent the device region;
• a plurality of active regions in the device region, wherein each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and wherein the first dimension is substantially greater than the second dimension;
• and
• a plurality of dummy active regions in the dummy region, wherein each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and wherein the third dimension is substantially greater than the fourth dimension,
• wherein the plurality of dummy active regions are all aligned with the plurality of active regions;
• wherein the first dimension of each of the active regions is parallel to the third dimension of each of the dummy active regions;
• and
• wherein the plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.