Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same

A device, comprising:

• first and second continuous active regions defined in a semiconducting substrate;
• first and second PFET transistors formed in and above said first continuous active region, each of said first and second PFET transistors comprising a plurality of P-doped regions formed in said first continuous active region and a gate electrode;
• first and second NFET transistors formed in and above said second continuous active region, each of said first and second NFET transistors comprising a plurality of N-doped regions formed in said second continuous active region and a gate electrode;
• a first conductive isolating electrode positioned above said first continuous active region between said first and second PFET transistors;
• a first power rail conductively coupled to said first conductive isolating electrode, wherein said first power rail is adapted to be at a logically high voltage level;
• a second conductive isolating electrode positioned above said second continuous active region between said first and second NFET transistors;
• and
• a second power rail conductively coupled to said second conductive isolating electrode, wherein said second power rail is adapted to be at a logically low voltage level.

A device, comprising:

• first and second continuous active regions defined in a semiconducting substrate, said first and second continuous active regions being separated by an isolation region;
• first and second PFET transistors formed in and above said first continuous active region, each of said first and second PFET transistors comprising a plurality of P-doped regions formed in said first continuous active region;
• first and second NFET transistors formed in and above said second continuous active region, each of said first and second NFET transistors comprising a plurality of N-doped regions formed in said second continuous active region;
• a first common gate electrode structure shared by said first PFET transistor and said first NFET transistor, said first common gate electrode extending across both of said first and second continuous active regions and said isolation region;
• a second common gate electrode structure shared by said second PFET transistor and said second NFET transistor, said second common gate electrode extending across both of said first and second continuous active regions and said isolation region;
• a first conductive isolating electrode positioned above said first continuous active region above a space between adjacent P-doped regions of said first and second PFET transistors;
• a first power rail conductively coupled to said first conductive isolating electrode, wherein said first power rail is adapted to be at a logically high voltage level;
• a second conductive isolating electrode positioned above said second continuous active region above a space between adjacent N-doped regions of said first and second NFET transistors;
• and
• a second power rail conductively coupled to said second conductive isolating electrode, wherein said second power rail is adapted to be at a logically low voltage level.