Thin film transistor array panel and manufacturing method thereof

A method for manufacturing a thin film transistor array panel, comprising:

• forming a gate electrode on a substrate;
• forming a gate insulating layer on the gate electrode;
• forming an oxide semiconductor layer on the gate insulating layer;
• forming a blocking layer on the oxide semiconductor layer;
• forming a metal layer on the blocking layer;
• forming a first photosensitive film pattern on the metal layer;
• etching the metal layer, the blocking layer, and the oxide semiconductor layer, using the first photosensitive film pattern as a mask, to form a metal layer pattern, a blocking layer pattern, and an oxide semiconductor layer pattern;
• performing an etch-back process on the first photosensitive film pattern, so as to form a second photosensitive film pattern that comprises an opening disposed above a channel region of the oxide semiconductor layer pattern;
• etching the metal layer through the opening, to form a source electrode and a drain electrode on the blocking layer;
• oxidizing a portion of the blocking layer pattern that is disposed above the channel region of the oxide semiconductor layer pattern, such that the oxide semiconductor layer pattern has a first portion that is not oxidized and a second portion that is oxidized;
• forming a passivation layer on the source electrode and the drain electrode;
• and
• forming a pixel electrode on the passivation layer, wherein,
• the first portion of the blocking layer pattern comprises a silicide or amorphous silicon,
• the second portion of the blocking layer pattern comprises silicon oxide (SiOx), and
• the silicon oxide (SiOx) content of the second portion is greater than the silicon oxide (SiOx) content of the first portion.