Integrated circuit wafer dicing method
AssigneeRaydium Semiconductor Corporation
InventorsChing-San Lin, Kun-Tai Wu, Chih-Chao Wang
Life of this patent
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Abstract
An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.
Claims5
An integrated circuit wafer dicing method, comprising:
- forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the test-keys are respectively disposed between the adjacent integrated circuits;
- forming a patterned protective layer on the integrated circuits, wherein the patterned protective layer covers the integrated circuits and exposes the test-keys;
- etching to remove the test-keys and to form a plurality of grooves at the locations of the test-keys by using the patterned protective layer as a mask, wherein the grooves have no contact with the integrated circuits;
- and
- dicing along the grooves to form a plurality of integrated circuit dies.
Dependencies are inferred from the claim text.