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US 8,617,955 B2Granted
Method and system for forming low contact resistance device
AssigneeVarian Semiconductor Equipment Associates, Inc.
InventorsAndrew Waite, Yuri Erokhin, Stanislav Todorov
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Abstract
A method of treating a CMOS device. The method may include providing a first stress liner on a transistor of a first dopant type in the CMOS device. The method may further include exposing the CMOS device to first ions in a first exposure, the first ions configured to reduce contact resistance in a source/drain region of a transistor of a second dopant type.
Claims7
A low contact resistance CMOS device, comprising:
- a first transistor of a first dopant type, the first transistor comprising;
- a source/drain region implanted with first ions, the first ions disposed at a first interface between a metallic contact and a semiconductor portion of a source/drain region of the first transistor, wherein the first ions are configured to lower a barrier height between the semiconductor portion and metallic contact;
- and
- a first stress liner of a first stress type;
- and
- a second transistor of a second dopant type, the second transistor having a second stress liner of a second stress type that includes implanted first ions.
3 more elements
A method of forming low contact resistance in a dual stress liner CMOS device, comprising:
- providing a first stress liner of a first stress type in a blanket deposition on the CMOS device;
- patterning the first stress liner to remove the first stress liner from a first transistor of a first dopant type disposed on a surface of the CMOS device;
- and
- exposing the CMOS device to first ions, wherein the first ions are implanted into a source/drain region of the first transistor, wherein the first ions are prevented from implanting into a source drain region of a second transistor of a second dopant type disposed on the surface of the CMOS device.
1 more element
Dependencies are inferred from the claim text.